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Adventurer
Adventurer
3,686 Views
Registered: ‎10-02-2014

HDMI 2.0 reference design timing violation

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Hello,

 

We just ordered a kintex 7 development board, we must implement an HDMI TX/RX system an it's on our plans

to aquire the HDMI ip.

While I'm waiting for the EVB to arrive i started looking at XAPP1287

Synthesizing with Vivado 2016.4 i got HOLD violations.

 

EG:

slack : -0.10   level : 1  fanout : 2 

from :  hdmi_example_kc705_i/v_hdmi_tx_ss_0/U0/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/lclk_fifo_dout_del_reg[42]/C 

to : hdmi_example_kc705_i/v_hdmi_tx_ss_0/U0/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH1_INST/VID_INST/lclk_lnk_reg[dat][1][2]/D  

 

This is a very big concern because, before allowing the purchase of the IP, I must be certain of the performance  and the portability on other targets.

 

I performed the implementation without modifying anything, so is there any advice I can get form xilinx about the HDMI IP core ?

Is a minimum design support included in the license fee in case we buy it?

 

Marco

 

 

 

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1 Solution

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Moderator
Moderator
6,373 Views
Registered: ‎11-09-2015

Re: HDMI 2.0 reference design timing violation

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Hi @marcoventurini,

 

For 2016.4, the xapps for HDMI have been replaced by the example design integrated inside vivado.

 

Please create right click on the IP and select open example design. If your project is on kc705, you will have the example project for this board and it should not have any timing issue.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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8 Replies
Moderator
Moderator
6,374 Views
Registered: ‎11-09-2015

Re: HDMI 2.0 reference design timing violation

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Hi @marcoventurini,

 

For 2016.4, the xapps for HDMI have been replaced by the example design integrated inside vivado.

 

Please create right click on the IP and select open example design. If your project is on kc705, you will have the example project for this board and it should not have any timing issue.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Explorer
Explorer
3,638 Views
Registered: ‎07-14-2014

Re: HDMI 2.0 reference design timing violation

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Marco,

 

I'm glad you have posted this, I was beginning to think it was just me, I have been working on the exact same problem but using the example design (not XAPP1287) and I too am getting a hold violation.

 

If i build without HDCP enabled, i get a single net with a WHS of ~-0.025ns. If I build with HDCP enabled (all generated as example design and nothing else done to it) I get 11 nets with a WHS of -0.1ns.

 

I too would love to know what is going wrong. Both designs built under Linux (Ubuntu 16.04) and with Vivado 2016.4.

 

Timing Summary attached.

 

Regards

 

Simon

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Xilinx Employee
Xilinx Employee
3,586 Views
Registered: ‎05-07-2015

Re: HDMI 2.0 reference design timing violation

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HI @simdav_dlp

 

Can you please send  a snapshot of your HDMI RXSS config GUI or the the xci file itself. so we can check the example design timing performance on KC705 at our end.

Thanks
Bharath
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Xilinx Employee
Xilinx Employee
3,559 Views
Registered: ‎07-31-2012

Re: HDMI 2.0 reference design timing violation

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Thanks for highlighting this. As discussed, use the example design from the IP rather than porting the XAPP. I hope you have selected KC705 board and not changed anything in the core apart from default XAPP XCI settings.

On the support, In case you do not have Service Request access then you would definitely be helped out with such issues here. However please post the XCI file and we will check and get back.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.
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Adventurer
Adventurer
3,550 Views
Registered: ‎10-02-2014

Re: HDMI 2.0 reference design timing violation

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With the example design I don't get violations, thanks a lot.

Maybe you should point out not to use it with recent Vivado versions.

I will try to add also HDCP now,

 

Thanks Again,

 

Marco

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Explorer
Explorer
3,484 Views
Registered: ‎07-14-2014

Re: HDMI 2.0 reference design timing violation

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XCI File attached as requested

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Visitor nikolamkg
Visitor
1,736 Views
Registered: ‎05-18-2018

Re: HDMI 2.0 reference design timing violation

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Hello,

 

I have been trying to use HDMI TX-only design example in Vivado 2018.1 on ZCU102 evaluation kit. I create design from HDMI TX component, I only change from pass-through topology to TX-only, other parameters are left with their initial values, but after running synthesis I get timing violations for a lot of paths. I have attached .rpx and .txt timing reports. I have been stuck with this problem for several days now, and it seems no one reports the same problem.

 

Thanks for reply.

 

Regards

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Moderator
Moderator
1,722 Views
Registered: ‎11-09-2015

Re: HDMI 2.0 reference design timing violation

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HI @nikolamkg

 

Our Community Help has a tip that might help you : Tip: If the message is older than 6-12 months, please post a new message rather than adding to the existing thread. Your inquiry will have a better chance of being picked up by an expert if it is a new topic.

 

https://forums.xilinx.com/t5/help/faqpage/faq-category-id/posting#posting

 

I would suggest you create a new topic on the appropriate board


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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