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Participant hariprasadb
Participant
603 Views
Registered: ‎04-23-2018

HDMI Audio loopback with DDR write and read

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Hello,

 

I am using HDMI RX and TX subsystem for Audio & video processing application using ZCU102 kit. I have some doubt with Audio interface to HDMI TX subsystem.

Initially I generted HDMI RX-TX loopbck example design and I observed the audio behaviour when HDMI RX is connected and not connected.

Then I have exported Audio out from HDMI RX and Audio In to HDMI TX subsystem and looped back in the top module & found the audio behaviour is fine.

Now I have written the Audio samples to PL DDR4 and reading from the same location. I am seeing the written and read audio samples are matching. I added ILA for Audio Write to DDR and read from DDR , the capture is exported to .csv files and compared the samples and written and read samples are matching. Currently I have retained the preamble and MSB 4 bits as  it is. DDR write and read happens burst of 128 words/samples at a time to DDR4. 

Then by seeing the Audio_tready from HDMI TX subsystem IP, I was simply sending the 32-bit samples with proper handling of tid(channel ID ) bus. Here I expected proper audio whichever I was playing in the source. But, hearing some noise although I send the proper samples.

To check the Audio sample handling, I was referring to Xilinx's Audio generator source code and found that each fream (subframe  0 & subframe 1) are sent for every 512 cycles but, not continuous. I followed the same but don't know the reason for the same.

Still the issue is not solved and same noise is played in HDMI monitor. 

Let me know any special consideration/synchronization to specific events to be made to handle the audio samples.

 

With Regards,

Hariprasad Bhat

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1 Solution

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Participant hariprasadb
Participant
471 Views
Registered: ‎04-23-2018

Re: HDMI Audio loopback with DDR write and read

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Hi,

 

Thank you for your suggestions.

I analyzed further and found that my logic was not pumping the valid data to HDMI TX subsystem. I corrected my DDR read logic and now able to hear the proper audio.

 

With Regards,

Hariprasad Bhat

6 Replies
Participant hariprasadb
Participant
577 Views
Registered: ‎04-23-2018

Re: HDMI Audio loopback with DDR write and read

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Hi,

 

I attached the ILA capture showing frame-1, frame-2 and continuous frame transfer to HDMI subsystem IP

 

With regards,

Hariprasad Bhat

audio_samples_to_TX_Subsystem.png
frame_2_samples.png
frame-1_samples.png
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Xilinx Employee
Xilinx Employee
508 Views
Registered: ‎08-02-2007

Re: HDMI Audio loopback with DDR write and read

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@hariprasadb

Do you have audio analyzer to analyze the audio? You have checked the audio samples, can you check if you have changed the sample rate of audio? Without PL DDR4, do you see this issue? Do you test L-PCM audio or HBR? Which version of Vivado are you using?

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Participant hariprasadb
Participant
472 Views
Registered: ‎04-23-2018

Re: HDMI Audio loopback with DDR write and read

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Hi,

 

Thank you for your suggestions.

I analyzed further and found that my logic was not pumping the valid data to HDMI TX subsystem. I corrected my DDR read logic and now able to hear the proper audio.

 

With Regards,

Hariprasad Bhat

Participant hariprasadb
Participant
424 Views
Registered: ‎04-23-2018

Re: HDMI Audio loopback with DDR write and read

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However, I am hearing some noisy amplitude coupled through out the  audio which I is played if I do DDR write and read. If I simply loopback this issue is not observed. The distinct noisy behaviour is identified if the loudness of the audio being played is more.

Does anybody encountered this issue? like generally if any sample missesd while writing to DDR and read from DDR could result this kind of behaviour?  Currently I am debugging my RTL which is used to write and read from DDR4.

With Regards,

Hariprasad Bhat

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Participant hariprasadb
Participant
358 Views
Registered: ‎04-23-2018

Re: HDMI Audio loopback with DDR write and read

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Hello, 

I was referring to some comments in the audio pattern generator code from Xilinx. I found below info in the code

// For 192 KHz, Audio Clock = 98.305 MHz, Count = 512
// For 176.4 KHz, Audio Clock = 90.3168 MHz, Count = 512
// For 96 KHz, Audio Clock = 49.152 MHz, Count = 512
// For 88.2 KHz, Audio Clock = 45.1584 MHz, Count = 512
// For 48 KHz, Audio Clock = 24.576 MHz, Count = 512
// For 44.1 KHz, Audio Clock = 22.5792 MHz, Count = 512
// For 32 KHz, Audio Clock = 16.384 MHz, Count = 512

Based on this, for every 512 cycles one frame is sent to HDMI TX subsystem, not continuosly. What is the logic behind it? What happens if we send the audio/pcm data as long as HDMI TX SS's Audio interface asserts ready?

With Regards,

Hariprasad Bhat

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Xilinx Employee
Xilinx Employee
345 Views
Registered: ‎08-02-2007

Re: HDMI Audio loopback with DDR write and read

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If you send your own audio through Audio Stream interface with correct timing (that shown in Figure 3-1 of PG235), it should work. In HDMI TX example, it only produces the beep sound, not real music through the audio channel.
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