HDMI Example Design from XAPP1287

[dolsen_xilinx]

Hi,

I am trying to get a particular format of video data to pass through the HDMI example design from XAPP1287 using the Kintex-7 KC705 board.

The example design works fine for me on a variety of video standards I tested, including 1080p60 and 4k60 (although the latter is a bit choppy). It doesn't seem to work on 1200x2160x90fps video data, though, which has a much lower data rate than 4k60.

Any idea what I would need to do to get this particular format data to play nice with the example design? Do I need to rebuild the design? If so, what should I be looking for - I didn't see any obvious settings that look to be of help in the IP Wizard, while following along with PG235.

Thank you,

Dave

[florentw]

Hi @dolsen_xilinx,

The xapp1287 has been replaced by the HDMI example design integrated in vivado. Check the chapter 5 of PG236 to know how to generate the example design.

This way you can have the most up-to-date example design.

Please try with it and let us know the result.

Regards,

[dolsen_xilinx]

Hi,

Thanks for your response. I used the PG235 example design in Vivado v2017.4 instead of PG236 because I'd already started going through it, and the instructions are almost identical. I hope that's fine.

I still get the same result, unfortunately. That is, it can pass video from my AppleTV and from an external HDMI connector on my laptop but not from the 1200x2160x90fps video source. Any other ideas?

Best regards,

Dave

[xud]

@dolsen_xilinx

If your resolution isn't in the pre-defined timing table, you need to add your own Video timing to Video Timing table. Please refer to AR below for more details :

https://www.xilinx.com/support/answers/68227.html

The other thing is to check the TMDS clock frequency, and see if it's in the QPLL/CPLL support range. What's the Horizontal Total and Vertical Total pixels for 1200x2160x90fps?

[watari]

Hi @dolsen_xilinx

Basically, video timing for HDMI should be followed CEA/EAI video timing or CVT video timing or CVT video timing formula.

In this case, Apple TV and your laptop are followed it. But the it seems that the "1200x2160x90fps" is not followed it.

I will make sure that this issue is video timing issue or not, if you show video timing (pixel clock frequency), as @florentw mentioned before.

Best regards,

[dolsen_xilinx]

Thank you for your replies.

The video source in this case is an Oculus Rift VR headset. The video frame is stereoscopic in nature, with one half dedicated for each eye. I'm not certain of the parameters in question nor where I would get them. 

Do you know what the specific parameters would be for the Oculus Rift? 

[watari]

Hi @dolsen_xilinx

Oculus Rift VR headset request two HDMI input. So, in this case the resolution on HDMI is 1200x1080 and it might be acceptable to output Xilinx's HDMI Tx IP even if frame rate is 90Hz. But you should consider pixel clock.

If you try it, I suggest to use the parameter which is modified from FHD video timing as 1200x1080@60Hz. (Only change horizontal active clock. Pixel clock is 148.5[MHz])

Best regards,

[dolsen_xilinx]

Hi,

Thanks for your help. I am looking into the software modifications you suggested.

On the hardware side - I'm not sure what you mean by: "Oculus Rift VR headset request two HDMI input". The headset only has one HDMI input. (The hardware in the headset separates out the video for the separate screens for the left and right eyes.) Can you clarify?

Also, to answer your question - according to my calculations I believe the TDMS clock should be: 278.4 MHz: 

i.e. 2160*1200*1.19*90fps/1,000,000;

...where 1.19 is the ratio of HDMI data *with* blanking to data *without* blanking for 1080p60.

That is: (1920+280)*(1080+45)/(1920*1080)=1.19. I assume I should use the same ratio here, but I could be wrong.

If I'm correct, this puts me in a "hole" in the QPLL range - at least according to Table 4 in XAPP1287. So, I think I need to use CPLLs instead. To that end, I tried to change the video PHY controller in the HDMI IP to use CPLL for both Tx and RX, but it won't let me.

Vivado says:

   Validation failed for parameter 'check pll selection(check_pll_selection)' with value '1' for BD Cell 'vid_phy_controller'

   PLL TYPE FOR BOTH TX AND RX SHOULD NOT SET TO SAME TYPE

Any ideas? Am I not able to support the required TDMS clock here?

Thank you,

Dave

[watari]

Hi @dolsen_xilinx

> On the hardware side - I'm not sure what you mean by: "Oculus Rift VR headset request two HDMI input". The headset only has one HDMI input. (The hardware in the headset separates out the video for the separate screens for the left and right eyes.) Can you clarify?

I thought it from data sheet. Normally, like this device use two video input. Because of interface has a limitation.

> Also, to answer your question - according to my calculations I believe the TDMS clock should be: 278.4 MHz: 

i.e. 2160*1200*1.19*90fps/1,000,000;

Maybe no.

HDMI Video timing contain blanking time to transfer like audio signal.

If possible, could you refer CEA video timing ?

Best regards,

[xud]

@dolsen_xilinx If you want to use CPLL for both TX and RX, you can set it in the terminal menu.

Note only 7 Series (including Zynq-7000) supports TX and RX in bonded mode. When you generate the Video PHY, you still need to use different type of PLL. If you use our example design (which is upgraded version for xapp1287), you can use menu "l" -> "3" if I remember correct to let both TX and RX use CPLL.

Also the blanking period to active period ratio might be different, it's better to contact Oculus and try to get the correct Video timing.

[florentw]

Hi @dolsen_xilinx,

Do you have any updates on this topic?

If everything is clear for you, please kindly close the topic by marking the best reply as accepted solution.

Thanks and Regards,

[dolsen_xilinx]

Not yet. Still trying to determine the video parameters for this. Data has not been forthcoming from manufacturer yet.

Will update soon.

Thank you,

Dave

[florentw]

Hi @dolsen_xilinx,

Still not update?

Regards,

[dolsen_xilinx]

Hi,

I believe I have the timing parameters now. 

Running the PG235 reference design, I obtained the following by intercepting the Oculus Rift video data in the Kintex-7 board:

   TX reference clock frequency:    296949760 Hz
   RX reference clock frequency:    296943616 Hz
   DRU reference clock frequency: 125000000 Hz

And, using a tool from Entech (www.entechtaiwan.com/util/moninfo.shtm) I was able to read the Modeline directly from the Oculus Rift headset:

   2160x1200p at 90Hz
   Modeline... "2160x1200" 296.950 2160 2168 2200 2240 1200 1250 1252 1473 +hsync -vsync

From this, you get the following:

   HDisp            2160 
   HSyncStart    2168
   HSyncEnd     2200
   HTotal            2240
   VDisp            1200
   VSyncStart    1250
   VSyncEnd     1252
   VTotal            1473

   [options]       +HSync -Vsync

...which *should* translate to these timing parameters:

   HSyncWidth = HSyncEnd - HsyncStart = 2200 - 2168 = 32
   HFrontPorch = HsyncStart - HDisp = 2168 - 2160 = 8
   HBackPorch = HTotal - HSyncEnd = 2240 - 2200 = 40

   VSyncWidth = VSyncEnd - VsyncStart = 1252 - 1250 = 2
   VFrontPorch = VsyncStart - VDisp = 1250 - 1200 = 50
   VBackPorch = VTotal - VSyncEnd = 1473 - 1252 = 221

And thus (per the table at the end of the following page: https://www.xilinx.com/support/answers/68227.html)

I derive the following values for the Xilinx HDMI example software timing parameters:

   1. ID XVIDC_VM_2160x1200_90_P
   2. Resolution Naming 2160x1200@90Hz
   3. Frame rate XVIDC_FR_90HZ
   4. Video timing structure
      1. Horizontal active resolution (pixels) 2160
      2. Horizontal front porch (pixels) 8
      3. Horizontal sync width (pixels) 32
      4. Horizontal back porch (pixels) 40
      5. Horizontal total (pixels) 2240
      6. Horizontal sync polarity (0=negative|1=positive) 1
      7. Vertical active resolution (lines) 1200
      8. Frame 0: Vertical front porch (lines) 50
      9. Frame 0: Vertical sync width (lines) 2
      10. Frame 0: Vertical back porch (lines) 221
      11. Frame 0: Vertical total (lines) 1473
      12. Frame 1: Vertical front porch (lines) 0
      13. Frame 1: Vertical sync width (lines) 0
      14. Frame 1: Vertical back porch (lines) 0
      15. Frame 1: Vertical total (lines) 0
      16. Vertical sync polarity (0=negative|1=positive) 0

And from the instructions on this same page, I replicated the code snippets they have provided as shown:

1.

   /* Assign Mode ID Enumeration. First entry Must be > XVIDC_VM_CUSTOM */
   typedef enum {
   XVIDC_VM_2160x1200_90_P= (XVIDC_VM_CUSTOM + 1),
       XVIDC_CM_NUM_SUPPORTED
   } XVIDC_CUSTOM_MODES;

2.

   /* Create entry for each mode in the custom table */
   const XVidC_VideoTimingMode XVidC_MyVideoTimingMode[(XVIDC_CM_NUM_SUPPORTED - (XVIDC_VM_CUSTOM + 1))]    =
   {
   { XVIDC_VM_2160x1200_90_P, "2160x1200@90Hz", XVIDC_FR_90HZ,
   {2160, 8, 32, 40, 2240, 1,
   1200, 50, 2, 221, 1473, 0, 0, 0, 0, 0} }
   };

3.

   /* User registers custom timing table */
     xil_printf("INFO> Registering Custom Timing Table with %d entries \r\n", (XVIDC_CM_NUM_SUPPORTED -    (XVIDC_VM_CUSTOM + 1)));
     Status = XVidC_RegisterCustomTimingModes(XVidC_MyVideoTimingMode, (XVIDC_CM_NUM_SUPPORTED -    (XVIDC_VM_CUSTOM + 1)));
     if (Status != XST_SUCCESS) {
         xil_printf("ERR: Unable to register custom timing table\r\n\r\n");
     }

However, it's not clear to me how to integrate these pieces of code into the software (assuming they're even correct). The instructions do not provide much detail on how to do this. Are you able to take what I have here and send me back the modified .c and/or .h files that I need to make this reference design work on the Oculus Rift?

Thank you,

Dave

[xud]

@dolsen_xilinx

Please see attached screenshot, showing you where to add the custom code, right side is xhdmi_example.c generated by HDMI example (detailed steps see chapter 5 of PG235/PG236). Left side is where you need to add custom definition

Following is an example showing you where to add bullet point 3 in your last reply :