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Adventurer
Adventurer
1,310 Views
Registered: ‎05-04-2014

HDMI TX IP bus skew problem

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Hi,

 

I generated HDMI passthrough example design and add MIG ip and bram ip. After I ran the design, vivado show the critical warning as below picture

1.PNG

2.PNG

And then I opened implemented design and used the bus skew report command 

3.PNG

I found all bus skew came from HDMI TX ip.

4.PNG

 

 The attached is my bus skew report. How do I fix it?

 

BR,

Sitting

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1 Solution

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Xilinx Employee
Xilinx Employee
1,290 Views
Registered: ‎08-02-2007

Re: HDMI TX IP bus skew problem

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@sitting

 

I used your dcp to generate timing summary, couldn't see any timing errors. Can you confirm if checkpoint is post-implementation? If so, I think you can ignore the warning.

13 Replies
Xilinx Employee
Xilinx Employee
1,299 Views
Registered: ‎03-30-2016

Re: HDMI TX IP bus skew problem

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Hello @sitting

from your report, I can see that all Endpoint Source/Destination & Reference Source/Destination are coming from the same module (XPM_GRAY_INST).

From:exdes_i/v_hdmi_tx_ss/U0/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/FIFO_INST/WP_CDA_INST/XPM_GRAY_INST/src_gray_ff_reg*
To:exdes_i/v_hdmi_tx_ss/U0/v_hdmi_tx/inst/SYS_INST/CORE_INST/CH2_INST/VID_INST/FIFO_INST/WP_CDA_INST/XPM_GRAY_INST/dest_graysync_ff_reg*

Could you try to add floor-planning restriction using pblock ? (please see UG906 Chapter 7 for detailed info)
Floorplanning may help your design to meet timing.

Best regards
Leo

XF_HDMI_TX_SKEW.png
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Adventurer
Adventurer
1,285 Views
Registered: ‎05-04-2014

Re: HDMI TX IP bus skew problem

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Hi @karnanl,

 

Do I restrict all the HDMI TX or only XPM_GRAY_INST?

 

Best regards

Sitting

 

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Xilinx Employee
Xilinx Employee
1,278 Views
Registered: ‎03-30-2016

Re: HDMI TX IP bus skew problem

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Hello @sitting

You can create floorplan with pblock for HDMI TX SS as a start-point.

Best regards
Leo

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Xilinx Employee
Xilinx Employee
1,273 Views
Registered: ‎08-02-2007

Re: HDMI TX IP bus skew problem

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@sitting

 

From the timing report, the source and destination are from different clock domains, the requirement is 3.367 ns. Can provide dcp and xdc file, so I can double check if the timing constraint is correct.  

Adventurer
Adventurer
1,245 Views
Registered: ‎05-04-2014

Re: HDMI TX IP bus skew problem

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Hi @xud,

 

Here are the download links:

DCPConstraint

 

BR,

Sitting

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Xilinx Employee
Xilinx Employee
1,218 Views
Registered: ‎08-02-2007

Re: HDMI TX IP bus skew problem

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@sitting

 

I have checked the dcp file, the pink route is the one has the problem. As link_clk and video_clk are both from the same PLL, they are related clock, vphy_clk.JPG

 

When I run report_clocks, both of them are constraints to 297MHz. For Video_CLK(vclk_from_txpll), it's correct.

For link_clk, 148.5Mhz should be enough. We have reported this issue.

report_clk.JPG

To improve timing, you can use normal timing closure, please try to use a different implementation strategy (eg. performance_explore), and see if it improves things.

 

Adventurer
Adventurer
1,207 Views
Registered: ‎05-04-2014

Re: HDMI TX IP bus skew problem

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Hi @xud,

 

I will try other implementation strategy. Which vivado version will fix this issue?  

 

 

 

Thanks

Sitting

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Adventurer
Adventurer
1,168 Views
Registered: ‎05-04-2014

Re: HDMI TX IP bus skew problem

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Hi @xud,

 

I have tried different implementation strategies, but bus skew problem is still exist. Waiting for your release of new patch seems the best way

 

BR,

Sitting

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Xilinx Employee
Xilinx Employee
1,093 Views
Registered: ‎08-02-2007

Re: HDMI TX IP bus skew problem

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No patch is needed, you can manually add constraint to constrain link_clk to 148.5 Mhz, following is an example, you probably need to change accordingly :

create_clock -name link_clk -period 6.734 [get_ports link_clk]

Adventurer
Adventurer
777 Views
Registered: ‎05-04-2014

Re: HDMI TX IP bus skew problem

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Hi @xud,

 

There are two constraints in video phy xdc as following:

create_clock -period 3.367 [get_pins -hier -filter {name=~*/XCVR_CH*_INST/gtxe2_i/TXOUTCLK}]









create_clock -period 3.367 [get_pins -hier -filter {name=~*/XCVR_CH*_INST/gtxe2_i/RXOUTCLK}]

Is it possible to change 3.367 to 6.734 directly?

 

BR,

Sitting

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Adventurer
Adventurer
765 Views
Registered: ‎05-04-2014

Re: HDMI TX IP bus skew problem

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Hi @xud,

 

I tried to change 3.367 to 6.734 directly and reran implementation. The bus skew issue was solved, but it generated new critical warning as following.

 

timing_2.PNG

I didn't see any timing issue in timing summary.

timing_3.PNG

 

Could you help me to check checkpoint as following link?

https://drive.google.com/open?id=1eQ8cRcVEmsy1vXgZ__sfSGRT0fuWVRA5

 

BR,

Sitting

 

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Xilinx Employee
Xilinx Employee
1,291 Views
Registered: ‎08-02-2007

Re: HDMI TX IP bus skew problem

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@sitting

 

I used your dcp to generate timing summary, couldn't see any timing errors. Can you confirm if checkpoint is post-implementation? If so, I think you can ignore the warning.

Adventurer
Adventurer
745 Views
Registered: ‎05-04-2014

Re: HDMI TX IP bus skew problem

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Hi @xud,

 

  I have checked it again, checkpoint is post-implementation. As you mentioned, I can ignore this critical warning.

 

BR,

Sitting

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