HDMI TX SS example

[msh]

Hello, 

In TX only example from Vivado for HDMI TX SS module is not supporting 4k resolution. When I select the 4K resolution in serial communication, I get the response negative as it can be seen below where I select 8 and 7.

---------------------------
---   RESOLUTION MENU   ---
---------------------------
 1 -  720 x 480p
 2 -  720 x 576p
 3 - 1280 x 720p
 4 - 1680 x 720p
 5 - 1920 x 1080p
 6 - 2560 x 1080p
 7 - 3840 x 2160p
 8 - 4096 x 2160p
 9 - 1920 x 1080i
10 -  640 x 480p (VGA / DMT0659)
11 -  800 x 600p (SVGA / DMT0860)
12 - 1024 x 768p (XGA / DMT1060)
13 - 1280 x 768p (WXGA / CVT1260E)
14 - 1366 x 768p (WXGA+ / DMT1360)
15 - 1280 x 1024p (SXGA / DMT1260G)
16 - 1680 x 1050p (WSXGA+ / CVT1660D)
17 - 1600 x 1200p (UXGA / DMT1660)
18 - 1920 x 1200p (WUXGA / CVT1960D)
19 - 1152 x 864p (Custom)
99 - Exit
Starting colorbar> 8
Unable to set requested TX video resolution.
Returning to previously TX video resolution.
VPHY Error: See log for details
Starting colorbar> 7
Unable to set requested TX video resolution.
Returning to previously TX video resolution.
VPHY Error: See log for details
Starting colorbar> 9
TX stream is down
TX stream is up
--------
Colorbar :
        Color Format:     RGB
        Color Depth:      8
        Pixels Per Clock: 2
        Mode:             Interlaced
        Frame Rate:       60Hz
        Resolution:       1920x1080@60Hz (I)
        Pixel Clock:      74250000
--------

May I know why is that? and how to overcome this problem to support 4K resolution? Where can I check log?

Thanking you 

Best regards

[florentw]

Hi @msh,

Basic question: Do you have any 4K monitor connected? The design won't sent 4K if the monitor cannot receive it. So it might be that your monitor only supports 1080p

[msh]

hi @florentw

I have Samsung U28E5908 model which supports 4K UHD (3840X2160)

https://www.1000ordi.ch/samsung-u28e590d-lu28e590ds_en-93334_fr.pdf

Best regards 

[msh]

hi @florentw

I also read the same problem here 

https://forums.xilinx.com/t5/Video/v-hdmi-tx-ss-0-ex-Unable-to-set-requested-TX-video-resolution/td-p/844153

It is solved via HDMI 2.0 DDC readback after 1920x1080x60p, but I do not know how to do so? 

also in the example project the encryption is disabled.

Thanks 

[msh]

Hi, 

here is the log that I able to find, where I can see that QPLL configuration is not found. How to solve this problem?

VPHY log
------
GT init start
GT init done
TX frequency event
TX timer event
TX MMCM reconfig done
QPLL reconfig done
GT TX reconfig start
GT TX reconfig done
QPLL lock
TX reset done
TX alignment done
Error! QPLL config not found!
VPHY Error: See log for details

[xud]

@msh

Do you see this problem on Xilinx board or your own board?

Normally Samsung TV has more than one HDMI socket, have you tried all of them. 

How do you drive the TX refclk? Normally this error occurs when the userclk frequency isn't correct or the clock jitter is too much.

Can you dump the Video PHY register? 

[msh]

@xud

Xilinx board : ZCU106

Yes I tried all the HDMI socket and tried sony monitor also (which supports 4K)

This is an example from Xilinx (which appears when we do right click and IP example). Though I see application clock from PS to be 300 Mhz. But maybe it is reconfigured via PS as the serial log states pixel clock 594 Mhz.

-----
Info
-----

------------
HDMI TX SubSystem
------------

  ->HDMI TX Subsystem Cores
    : HDMI TX 
    : VTC Core 
  HDMI TX version : 03.00 (0401)
  VTC version is not available for reading as HDMI TX Video Clock is not ready.

HDMI TX timing
------------
HDMI TX Mode - HDMI 
HDMI Video Mask is Disabled

        Color Format:     RGB
        Color Depth:      8
        Pixels Per Clock: 2
        Mode:             Progressive
        Frame Rate:       60Hz
        Resolution:       3840x2160@60Hz
        Pixel Clock:      594000000

        HSYNC Timing: hav=3840, hfp=176, hsw=88(hsp=1), hbp=296, htot=4400 
        VSYNC Timing: vav=2160, vfp=08, vsw=10(vsp=1), vbp=072, vtot=2250
Scrambled: 0
Sample rate: 0

Audio
---------
Format   : L-PCM
Channels : 0
------------
HDMI PHY
------------
  VPhy version : 02.02 (0000)

GT status
---------
TX reference clock frequency: 0 Hz
TX: QPLL0
RX: CPLL
TX state: idle
RX state: idle

QPLL0 settings
-------------
M : 0 - N : 0 - D : 0

CPLL settings
-------------
M : 0 - N1 : 0 - N2 : 0 - D : 0

RX MMCM settings
-------------
Mult : 0 - Div : 0 - Clk0Div : 0 - Clk1Div : 0 - Clk2Div : 0

TX MMCM settings
-------------
Mult : 0 - Div : 0 - Clk0Div : 0 - Clk1Div : 0 - Clk2Div : 0

DRU Settings
-------------
Version  : 7
DRU is disabled

Also, when I run below code, I get into else statement. Which I think is not correct as the monitor supports 4K.

XV_HdmiTxSs_DetectHdmi20(&HdmiTxSs);
if (HdmiTxSs.HdmiTxPtr->Stream.IsHdmi20)
 xil_printf("HdmiTxSs->HdmiTxPtr->Stream->IsHdmi20 = 1.\r\n");
else
 xil_printf("\x1b[31mHdmiTxSs->HdmiTxPtr->Stream->IsHdmi20 = 0.\r\n\x1b[0m");
break;

There is no register dump. Maybe because I am using trial version license.

 

Please let me know how can I resolve this problem?

Thanks 

[msh]

@xud @florentw

I would like to give additional information. I see these warning in serial out when I check EDID:

Warning: Connected Sink's EDID indicates HDMI 2.0 capable, but the SCDC read request register bit 
(VSDB:RR_Capable) is not asserted
Warning: Connected Sink's EDID indicates HDMI 2.0 capable, SCDC present and capable of initiating 
read request, however the SCDC is inaccessible
Warning: Connected Sink's EDID indicates Deep Color of 10 BpC Not Supported
Warning: Connected Sink's EDID indicates Deep Color of 12 BpC Not Supported
Warning: Connected Sink's EDID indicates Deep Color of 16 BpC Not Supported

Here is the proof that HDMI 2 support 4K with 60 Hz in Samsung monitor

[msh]

Info reply on 4K HDMI2 

-----
Info
-----

------------
HDMI TX SubSystem
------------

  ->HDMI TX Subsystem Cores
    : HDMI TX 
    : VTC Core 
  HDMI TX version : 03.00 (0401)
  VTC version     : 06.01 (000B)

HDMI TX timing
------------
HDMI TX Mode - HDMI 
HDMI Video Mask is Disabled

        Color Format:     RGB
        Color Depth:      8
        Pixels Per Clock: 2
        Mode:             Progressive
        Frame Rate:       60Hz
        Resolution:       3840x2160@60Hz
        Pixel Clock:      594000000

        HSYNC Timing: hav=3840, hfp=176, hsw=88(hsp=1), hbp=296, htot=4400 
        VSYNC Timing: vav=2160, vfp=08, vsw=10(vsp=1), vbp=072, vtot=2250
Scrambled: 0
Sample rate: 1

Audio
---------
Format   : L-PCM
Channels : 2
------------
HDMI PHY
------------
  VPhy version : 02.02 (0000)

GT status
---------
TX reference clock frequency: 198004736 Hz
TX: QPLL0
RX: CPLL
TX state: ready
RX state: idle

QPLL0 settings
-------------
M : 1 - N : 80 - D : 8

CPLL settings
-------------
M : 0 - N1 : 0 - N2 : 0 - D : 0

RX MMCM settings
-------------
Mult : 0 - Div : 0 - Clk0Div : 0 - Clk1Div : 0 - Clk2Div : 0

TX MMCM settings
-------------
Mult : 8 - Div : 1 - Clk0Div : 16 - Clk1Div : 8 - Clk2Div : 16

DRU Settings
-------------
Version  : 7
DRU is disabled

info reply on 2K HDMI2

-----
Info
-----

------------
HDMI TX SubSystem
------------

  ->HDMI TX Subsystem Cores
    : HDMI TX 
    : VTC Core 
  HDMI TX version : 03.00 (0401)
  VTC version     : 06.01 (000B)

HDMI TX timing
------------
HDMI TX Mode - HDMI 
HDMI Video Mask is Disabled

        Color Format:     RGB
        Color Depth:      8
        Pixels Per Clock: 2
        Mode:             Progressive
        Frame Rate:       60Hz
        Resolution:       2560x1080@60Hz
        Pixel Clock:      198000000

        HSYNC Timing: hav=2560, hfp=248, hsw=44(hsp=1), hbp=148, htot=3000 
        VSYNC Timing: vav=1080, vfp=04, vsw=05(vsp=1), vbp=011, vtot=1100
Scrambled: 0
Sample rate: 1

Audio
---------
Format   : L-PCM
Channels : 2
------------
HDMI PHY
------------
  VPhy version : 02.02 (0000)

GT status
---------
TX reference clock frequency: 198002688 Hz
TX: QPLL0
RX: CPLL
TX state: ready
RX state: idle

QPLL0 settings
-------------
M : 1 - N : 80 - D : 8

CPLL settings
-------------
M : 0 - N1 : 0 - N2 : 0 - D : 0

RX MMCM settings
-------------
Mult : 0 - Div : 0 - Clk0Div : 0 - Clk1Div : 0 - Clk2Div : 0

TX MMCM settings
-------------
Mult : 8 - Div : 1 - Clk0Div : 16 - Clk1Div : 8 - Clk2Div : 16

DRU Settings
-------------
Version  : 7
DRU is disabled
 

Please let me know if this gives any clue.

Thank you 

Best regards 

[xud]

@msh

The clock isn't configured properly. For 4Kp60 RGB, the TX reference clock should be running at 148.5 MHz(594MHz/4)

Your TX reference clock frequency: is running at 200Mhz.

How do you driver TX reference clock ? Have you configure it to 148.5 MHz?

You can firstly switch TX to DVI mode, so you don't need to worry about SCDC read request register bit  warning.

The issue is still related to Video PHY. it's very important to print out the register dump. Following is an example to dump VPHY register dump in xsct command line :

"mrd 0x44A40000 200"

0x44A40000 should be changed to the base address of Video PHY in your design. You can find it in Address Editor Tab when you open IPI.

I don't see any reason why you can't dump it.

[msh]

Hi, 

The TX reference clock is given by SFP_SI5328_OUT_C_P. 

I think so it is configured to 148.5 as 2K resolutions are working. I dont know how to find the what is configuration is for 4K. I am using HDMI example from Xilinx (TX only). 

Here is the base address of VPHY:

/* Definitions for driver VPHY */
#define XPAR_XVPHY_NUM_INSTANCES 1

/* Definitions for peripheral VID_PHY_CONTROLLER */
#define XPAR_VID_PHY_CONTROLLER_DEVICE_ID 0
#define XPAR_VID_PHY_CONTROLLER_BASEADDR 0x80060000
#define XPAR_VID_PHY_CONTROLLER_TRANSCEIVER_STR "GTHE4"

When I try it on XSCT:

mrd 0x80060000 200
xsct% Memory read error at 0x80060000. PL AXI slave ports access is not allowed. This address has not beed added to the memory map

[msh]

Hi, 

TX reference clock should be running at 148.5 MHz(594MHz/4):

Does this line from you means 4 pixels per clock ?? Because I see in the info that it is 2 pixels per clock.

Best regards 

[xud]

@msh

Please take a look at Chapter 3 -> Clocking at PG235 on how to calculate the clock frequency.

When Line rate > 3.4G, we use factor 4*TMDS Clock = Pixel clock. No matter it's 4 ppc or 2 ppc.

From your log file, TX ref clock is always 198 Mhz. We need to check a few things :

1. AXI Lite interface of Video PHY is driven by Processor. As you can't dump the register value, you probably need to check the connection of AXI lite interface, and also if there is no clock for AXI lite interface of Video PHY or it's still under reset status.

2. Tx_refclk_rdy toggles after you change the resolution. As for the fact the TX ref clock doesn't change, I also doubt whether you have toggled it. if you don't toggle it, the tx frequency event interrupt won't be triggered. Video PHY won't know if you have switched the resolution, or sink has been changed.

3. If 2k resolution works fine, Samsung TV should be able to display image in 2k mode. But you can't seen anything, I suspect the issue is to do with tx_refclk_rdy. If it's asserted before tx refclk is stable, it can cause Video PHY hang.

[tim_severance]

@msh,

   Are you using the KC705 hardware with the Inrevium HDMI FMC card?   If so did you try generating the example design and generating the example SDK project and use that project as-is or have you modified it?   The example project with KC705 has never given me any problems and is always a good working reference.   

Tim

[msh]

Hi,
1. AXI lite is connected thats why there is a base address in xparameter file.
2. TX refclk toggle is connected to SI5324_LOL_IN. Hence I am not changing it.
3. 2K works fine. It can display.

[msh]

@tim_severance

I am using ZCU106 board from Xilinx. I directly use the example (by right click on HDMI and create example project) and then add files from xilinx SDK directory (Tx only exmple for HDMItxss)

And this is the problem I am facing. It seems that Txrefclock is not configured properly in the example.

Best regards

[msh]

@tim_severance @xud

I would like to share SDK project, please find in attachment.

[tim_severance]

@msh,

   I have never used that board myself.  

   Have you tried: 1) different HDMI cable (i.e. one made for 4K 60hz operation), 2) multiple 4K compatible TVs/monitors?   I ask because both of these have been issues for me.  I have had cables that worked for everything but 4k60p and also monitors that always work right away at 4K and some that give me issues, for example the Lilliput in my other post caused me to need to add that additional code to get 4K working.   

Tim

[tim_severance]

@msh,

   Also what Vivado/SDK version are you using?    And you say you copied the example project from the SDK directory.  Did you copy this manually, or did you click on the generate example link from within SDK itself?    I always do it all from SDK (I.e. no manual copying of files).   

Tim

[msh]

Hi ,
Yes, I tried different monitors and also posted a photo in which monitor is supporting 4k@60 if I connect it to PC(GPU) and change Nvidia settings for display.

[msh]

Hi,
Yes, I import project files from Xilinx SDK directory.
C:\Xilinx\SDK\2018.1\data\embeddedsw\XilinxProcessorIPLib\drivers\v_hdmitxss_v5_0\examples\xhdmi_example

All the files + TxOnly folder.

I suppose this should work. There should be the difference between importing the project and get an example to generate.

Best regards

[tim_severance]

@msh,

   I would recommend trying it from SDK itself, especially since you are experiencing issues. 

   Also, did you try the cables and monitors I mentioned?

Tim

[msh]

Yes, I changed the cable and monitor before and it didn't work. I posted the VPHY log and EDID warning.

how can I generate example from SDK itself? I thought example files need to be imported.

[msh · Accepted solution]

@tim_severance@xud

I don't know why it behaved such.

I just put these lines in the place where it is shown in the code 

xil_printf("IsStreamUp %d\n",IsStreamUp);
xil_printf("SinkReady %d\n",SinkReady);

		if (IsStreamUp && SinkReady) {
			xil_printf("IsStreamUp %d\n",IsStreamUp);
			xil_printf("SinkReady %d\n",SinkReady);
			IsStreamUp = FALSE;
			i2c_dp159(&Vphy, 0, TxLineRate);
			XVphy_Clkout1OBufTdsEnable(&Vphy, XVPHY_DIR_TX, (TRUE));
		}

Then I put below line in enablecolorbar function, just before the I2CCLK call.

xil_printf("VphyPtr->HdmiTxRefClkHz %d \n", VphyPtr->HdmiTxRefClkHz);

Now 4k works. I don't know why !!!! the print statement shouldn't make any difference. 

Info on 4K now:

-----
Info
-----

------------
HDMI TX SubSystem
------------

  ->HDMI TX Subsystem Cores
    : HDMI TX 
    : VTC Core 
  HDMI TX version : 03.00 (0401)
  VTC version     : 06.01 (000B)

HDMI TX timing
------------
HDMI TX Mode - HDMI 
HDMI Video Mask is Disabled

        Color Format:     RGB
        Color Depth:      8
        Pixels Per Clock: 2
        Mode:             Progressive
        Frame Rate:       60Hz
        Resolution:       3840x2160@60Hz
        Pixel Clock:      594000000

        HSYNC Timing: hav=3840, hfp=176, hsw=88(hsp=1), hbp=296, htot=4400 
        VSYNC Timing: vav=2160, vfp=08, vsw=10(vsp=1), vbp=072, vtot=2250
Scrambled: 1
Sample rate: 1

Audio
---------
Format   : L-PCM
Channels : 2
------------
HDMI PHY
------------
  VPhy version : 02.02 (0000)

GT status
---------
TX reference clock frequency: 148500480 Hz
TX: QPLL0
RX: CPLL
TX state: ready
RX state: idle

QPLL0 settings
-------------
M : 1 - N : 80 - D : 2

CPLL settings
-------------
M : 0 - N1 : 0 - N2 : 0 - D : 0

RX MMCM settings
-------------
Mult : 0 - Div : 0 - Clk0Div : 0 - Clk1Div : 0 - Clk2Div : 0

TX MMCM settings
-------------
Mult : 10 - Div : 1 - Clk0Div : 5 - Clk1Div : 10 - Clk2Div : 5

DRU Settings
-------------
Version  : 7
DRU is disabled

2K info 

-----
Info
-----

------------
HDMI TX SubSystem
------------

  ->HDMI TX Subsystem Cores
    : HDMI TX 
    : VTC Core 
  HDMI TX version : 03.00 (0401)
  VTC version     : 06.01 (000B)

HDMI TX timing
------------
HDMI TX Mode - HDMI 
HDMI Video Mask is Disabled

        Color Format:     RGB
        Color Depth:      8
        Pixels Per Clock: 2
        Mode:             Progressive
        Frame Rate:       60Hz
        Resolution:       3840x2160@60Hz
        Pixel Clock:      594000000

        HSYNC Timing: hav=3840, hfp=176, hsw=88(hsp=1), hbp=296, htot=4400 
        VSYNC Timing: vav=2160, vfp=08, vsw=10(vsp=1), vbp=072, vtot=2250
Scrambled: 1
Sample rate: 1

Audio
---------
Format   : L-PCM
Channels : 2
------------
HDMI PHY
------------
  VPhy version : 02.02 (0000)

GT status
---------
TX reference clock frequency: 148500480 Hz
TX: QPLL0
RX: CPLL
TX state: ready
RX state: idle

QPLL0 settings
-------------
M : 1 - N : 80 - D : 2

CPLL settings
-------------
M : 0 - N1 : 0 - N2 : 0 - D : 0

RX MMCM settings
-------------
Mult : 0 - Div : 0 - Clk0Div : 0 - Clk1Div : 0 - Clk2Div : 0

TX MMCM settings
-------------
Mult : 10 - Div : 1 - Clk0Div : 5 - Clk1Div : 10 - Clk2Div : 5

DRU Settings
-------------
Version  : 7
DRU is disabled

If anyone knows the explanation, then please let me know.

Thank you 

Best regards 

[tim_severance]

@msh,

   Glad it worked!

   See below for how to generate example applications from within SDK:

Tim

[xud]

@msh

As far as I know Si5328 is very slow to get locked, normally it takes a few second.

probably adding additional xil_printf brings additional delays so hardware can be ready.

[msh]

Thank you for the suggestion :D

[msh]

it will be good if it is mentioned in the example document or example updated for next release.

Thanks

[xud]

@msh

Issue is related to Si5328, this clock cleaner has a much lower loop bandwidth than the other clock cleaners in the Si532x family.

Not only HDMI based application, other IPs like JESD, CPRI based application has this problem as well.

We have mentioned it in the tx_refclk_rdy requirement of PG230. Also it doesn't mention how slow external clock generator can be, but it does mention that the variation of  tx_refclk_rdy could be :

"It can ONLY be asserted when the clock at txrefclk_p/n port is stable.

At AXILITE CLK = 100 MHz, the tx_refclk_rdy minimum hold time are 5us and 4ms for fast switching and non-fast switching modes respectively.

TX REFCLK frequency detection is sensitive only to the behavior of the tx_refclk_rdy port, which triggers the Clock Detector to issue the TX frequency change event. This is because users program the external clock generator for the desired clock frequency in the

TX operation, which means that the VPHY TX should get the requested frequency from the clock generator. Because the assumption is that VPHY gets the correct clock, it only requires the LOCK event to trigger the TX reconfiguration which is represented by the assertion of tx_refclk_rdy.

"