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Explorer
Explorer
737 Views
Registered: ‎08-31-2016

HDMI : Video PHY Controller Line Rate for different resolutions

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Hi,

 

How does the line rate taken care for the Video PHY controller in HDMI Applications?

 

I set the maximum line rate supported to ~5.9 Gbps in the Video PHY configuration GUI. I would like to know how will the system (VPHY) come to know about different resolutions (HD,FHD or UHD)  &  facilitate the line rate change?

 

Regards,

Vinay

Vinay Shenoy
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Xilinx Employee
Xilinx Employee
676 Views
Registered: ‎08-02-2007

Re: HDMI : Video PHY Controller Line Rate for different resolutions

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@vinay_shenoy

 

From you description, it seems that you are more interested at TX side.

 

Please take a look at, Figure 3-11, Table 3-3 of PG236 and the example after this table : https://www.xilinx.com/support/documentation/ip_documentation/v_hdmi_rx_ss/v3_1/pg236-v-hdmi-rx-ss.pdf

 

It gives details on how link clock is associated to the line rate. example shows how color information is associated to the different clocks.

 

You need to ensure the TX refclk is running at the required frequency. In our example design, there is I2C API to control onchip clock generator, let it generate expected frequency.  Then Video PHY driver can configure the PLL and MMCM parameters to generate Link clock and video clocks, and supply them to HDMI IP.

 

4 Replies
Xilinx Employee
Xilinx Employee
687 Views
Registered: ‎08-02-2007

Re: HDMI : Video PHY Controller Line Rate for different resolutions

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@vinay_shenoy 

 

There is Clock detector module inside Video PHY. At TX side, tx_refclk_rdy triggers this module, and tells video PHY there is a clock frequency change. Then Video PHY starts to re-configure the clock based on the color information configured by driver.

 

At RX side, clock detector will capture the RX frequency from RX TMDS clock (when DRUCLK isn't used), and check if it's stable for the whole video frame, if it does, then it issues frequency lock and reports the RX frequency. You can get the RX frequency value  from Video PHY register 0x0210

 

Explorer
Explorer
683 Views
Registered: ‎08-31-2016

Re: HDMI : Video PHY Controller Line Rate for different resolutions

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So it's the Video PHY that starts to re-configure the link clock based on the color information configured by driver. 

 

And depending on this link clock, the line rate will change. Isn't it?

 

Thank you @xud

Vinay Shenoy
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Xilinx Employee
Xilinx Employee
677 Views
Registered: ‎08-02-2007

Re: HDMI : Video PHY Controller Line Rate for different resolutions

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@vinay_shenoy

 

From you description, it seems that you are more interested at TX side.

 

Please take a look at, Figure 3-11, Table 3-3 of PG236 and the example after this table : https://www.xilinx.com/support/documentation/ip_documentation/v_hdmi_rx_ss/v3_1/pg236-v-hdmi-rx-ss.pdf

 

It gives details on how link clock is associated to the line rate. example shows how color information is associated to the different clocks.

 

You need to ensure the TX refclk is running at the required frequency. In our example design, there is I2C API to control onchip clock generator, let it generate expected frequency.  Then Video PHY driver can configure the PLL and MMCM parameters to generate Link clock and video clocks, and supply them to HDMI IP.

 

Moderator
Moderator
616 Views
Registered: ‎11-09-2015

Re: HDMI : Video PHY Controller Line Rate for different resolutions

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Hi @vinay_shenoy,

 

Was the reply from @xud enough for you?

 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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