07-31-2018 11:23 PM
Performing small experiment on ZCU106 to start for image processing applications. I will be loading image of size 256 x 256 in BRAM as .coe file and then want to display image on HDMI interface. I am using HDMI Tx subsystem and Video PHY controller IP to interface with HDMI port.
I am not able to route some connection of these IPs. I have attache image of block design. Which connection will come to s_AXI_CPU_in of HDMI tx ss IP and axi4lite port of Video PHY controller IP. Video IN input signals will be routed from top module with the data coming from BRAM.
08-01-2018 07:00 AM
I suggest taking a look at XAPP1291 to see an example of using the HDMI TX subsystem and the Video PHY controller. Since you are using a ZCU106 board you will want to substitute the ARM PS for the MicroBlaze that is used in the XAPP.
08-01-2018 07:27 AM - edited 08-01-2018 07:31 AM
Using a reference design as mentioned by @tedbooth is usually a good start. However, please do not use the xapp1291 as it is deprecated.
There is an example design for ZCU106 you can generate with vivado. Refer to PG236 chapter 5.
However, I think in your case you are missing an IP to grab the data from memory and convert it it AXI4-Stream. You might want to look at the VDMA or frame buffer read/write.
08-22-2018 03:13 AM
Do you have any updates on this? Did the reply from @tedbooth helped you?
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