03-08-2018 06:25 PM
I have an HDMI design that I am troubleshooting working with some displays and not others and I was hoping somebody could give me some tips or point me to a good resource.
I am trying to get 4K 60Hz HDMI 2.0 working and I have a TV that I plug into and everything works fine. The EDID reads fine and the DDC readsback that the display is HDMI 2.0 compatible and video works. But I have another display (lilliput A12) that will not work.
One issue I know I have with my hardware is that I do not have a level translator between the FPGA DDC pins and the HDMI connection, so the DDC levels are 3.3V logic instead of 5V, but the EDID of the lilliput seems to read just fine which makes me think things are ok.
The interesting thing is that when reading the EDID device address 0x50 the lilliuput ACKs, but when trying to read if the monitor is HDMI 2.0 capable (also reading device address 0x50) the Lilliput NACKs. This is confusing to me. So I am guessing because I cannot read HDMI 2.0 capability and I cannot set scrambling settings the monitor will not work at 4K 60Hz.
Does anybody know of a good resource for getting to know all HDMI requirements?
Any help here is appreciated.
04-10-2018 03:45 AM
03-08-2018 06:50 PM
You can find the Board Design Guidelines for HDMI in PG230. You must have a Level Shifter in order to be HDMI Compliant, and it is likely this is the reason you are not seeing consistent results. The higher the data rate the more important the Level Shifter is for the Data lines. But it is also important for the DDC as you pointed out, if you can't negotiate the link it can cause issues as well. You might be able to force a resolution if the problem is only with the DDC, but since you are trying to output at 4Kp60, it is likely to also be an issue on the data lines as well.
The recommended Level Shifter is the Texas Instruments SN65DP159 for HDMI 2.0, as noted in PG230.
03-08-2018 06:58 PM
Thanks for the reply. I am using the DP159 as a tmds level shifter and it is working great for that. I think the only problem seems to be the DDC. Do you recommend using the DP159 as both the TMDS and DDC level shifters?
03-08-2018 07:57 PM
Yes, you should pass the DDC lines through the Ti DP159 as well. You can look at the ZCU102 Schematic which can be found on the ZCU102 Design Hub.
You should also make sure that you are using Ti DP159 production silicon (not ES). See AR70515 (Should be available in the next 24 hours.)
03-10-2018 07:51 AM
03-10-2018 10:16 AM
By the way I just ran across AR#69427 (https://www.xilinx.com/support/answers/69427.html) which mentions a known issue with DDC sinks requesting clock stretch. I am currently using Vivado 2017.4 with HDMI Version 3.0 (rev 1). Do you know if the clock stretching issue was fixed in this version? And if not, can I manually dig into the design to increase the timeout to avoid the problem?
03-12-2018 06:42 AM
03-19-2018 04:20 AM
If everything is clear for you on this subject, please kindly mark a reply as solution to close the topic. Else please reply to the topic
Thanks and Regards,
03-19-2018 07:43 AM
You mention that the AR#69427 should be fixed in 2017.3 and later, but the AR does not mention that it actually has been fixed. I am suspicious that this might be part of my problem getting the DDC to properly work even with a level translator installed.
03-19-2018 06:52 PM
> The interesting thing is that when reading the EDID device address 0x50 the lilliuput ACKs, but when trying to read if the monitor is HDMI 2.0 capable (also reading device address 0x50) the Lilliput NACKs.
I'm not sure. But E-EDID address is changed from 0x50 to 0xA0 and 0xA1 when it is HDMI 2.0.
Could you make sure it ?
03-23-2018 07:42 AM
03-23-2018 07:50 AM
04-09-2018 04:29 AM
@tim_severance I still feel the issue could be related to the DDC power. Even if you can read EDID register fine, but you don't have enough power, so the response(acknowledge) time on I2C could be slower.
The spec also requires read request only remains active when +5V Power signal is provided. If you don't follow the spec, I don't know how much more suggestion we can offer.
If you have HDMI/I2C analyser, you can capture the trace log for TX DDC interface, and compare the working Sink, and non-working Sink, then you can get more hints.
04-09-2018 09:04 AM
We can close this for now. If I determine the issue down the road after I do get an HDMI analyzer in my hands I will try to remember to update this thread with what the problem was.
Thanks for your help.
04-10-2018 01:55 AM
To close this topic, could you mark a reply as accepted solution?
04-10-2018 03:45 AM