10-03-2019 08:19 AM - edited 10-03-2019 01:33 PM
I am trying to port a video controller module over to US+ from a working Zynq design in Vivado 2019.1. The older design used an 800x600 LCD screen; the new design uses a 1024x600 LCD screen.
I am getting video to appear on my screen, but the data being sent is interspersed with 0x00000000, like so:
The problem shown in this waveform is borne out on the screen by having one correctly displayed 0x00FF00FF pixel and one black 0x00000000 pixel.
A detail of my block diagram:
Per the AXI VDMA guide advice, my synchronous VDMA has its ACLKs all tied to the same 150 MHz fabric clock. (However, the original working Zynq project had the s_axi_lite_aclk tied to a 75 MHz fabric clock and the m_axi*_mm2s_aclk signals tied to a separate150 MHz fabric clock; I've tried this configuration and it did work.)
I understand the FPGA side far better than the PS side code, but I am not toally convinced this isnt a PL-side IP configuration problem.
My IP configuration screens:
The video data is coming out of the VDMA block with the unwanted 0x00000000 pixels. Upstream of that, I'm having trouble tracing the problem.
Vivado video experts, are there any obvious configuration issues?
10-09-2019 01:11 AM
Can you configure the timing from the Static Video Timing Generator? Else this is what you are missing first.
You might want ot have a look at my Video Series for basics of Video Design. Specifically the following ones can be useful: