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Scholar watari
Scholar
893 Views
Registered: ‎06-16-2013

How to do simulation my design with v_tc (Video Timing Controller), ZYNQ VIP and AXI VIP ?

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Hi all

I already posted my question at other category. (https://forums.xilinx.com/t5/AXI-Infrastructure/How-do-I-execute-post-synthesis-functional-simulation-with-AXI/m-p/845739)
However, I can not resolve it.

Then, I modified my question and post my question again.
Would anyone help me ?

---
I'd like to clarify my understanding about the behavior of v_tc (video timing controller) by simulation.
However it seems protected IP. I can't pick up some signals under 2nd layer. I can pick up just IP top layer's signals.

[Question]
Q1) How do I pick up some signals under 2nd layer ?
Q2) If, Q1's anser is no, I'd like to do simulation with post synthesis functional simulation by xsim with AXI VIP and ZYNQ VIP. However AXI VIP and ZYNQ VIP can not be supported for post synthesis functional simulation mode. Do you have any idea to resolve my issue. How do I do to resoluve my question ?

Best regards

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Xilinx Employee
Xilinx Employee
1,163 Views
Registered: ‎08-02-2007

Re: How to do simulation my design with v_tc (Video Timing Controller), ZYNQ VIP and AXI VIP ?

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@watari

 

It's more related to simulation.

 

You need to generate the post-synthesis simulation model from Video Timing dcp file firstly, and then add the post-synthesis simulation model as simulation only source to the project.

 

In that case, you should be able to use behavioral for VIP, but post-synthesis simulation mode for Video Timing Controller.

 

It's easier to do it using Modelsim, as you only need to modify the compile list in the do file, and use the post-synthesis simulation mode file name to replace behavioral simulation model name.

 

Or you can generate dcp for Video Timing controller in advance, and then package the dcp file as a custom IP, brings it to IPI, Vivado tool should use structural mode for simulation in this way.

3 Replies
Moderator
Moderator
865 Views
Registered: ‎11-09-2015

Re: How to do simulation my design with v_tc (Video Timing Controller), ZYNQ VIP and AXI VIP ?

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Hi @watari,

 

Q1. I do not think there is any real solution to this in simulation. On thing you could do is to add an ILA on the internal signals in the synthesized design and run it in HW

 

Q2. The VIP should be synthesized as wire. I am not sure why you need to use the Zynq VIP here. For the VIP, you might be able to add it in your test bench (which won't be synthesized).

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Xilinx Employee
Xilinx Employee
1,164 Views
Registered: ‎08-02-2007

Re: How to do simulation my design with v_tc (Video Timing Controller), ZYNQ VIP and AXI VIP ?

Jump to solution

@watari

 

It's more related to simulation.

 

You need to generate the post-synthesis simulation model from Video Timing dcp file firstly, and then add the post-synthesis simulation model as simulation only source to the project.

 

In that case, you should be able to use behavioral for VIP, but post-synthesis simulation mode for Video Timing Controller.

 

It's easier to do it using Modelsim, as you only need to modify the compile list in the do file, and use the post-synthesis simulation mode file name to replace behavioral simulation model name.

 

Or you can generate dcp for Video Timing controller in advance, and then package the dcp file as a custom IP, brings it to IPI, Vivado tool should use structural mode for simulation in this way.

Scholar watari
Scholar
807 Views
Registered: ‎06-16-2013

Re: How to do simulation my design with v_tc (Video Timing Controller), ZYNQ VIP and AXI VIP ?

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Hi @xud

 

Sorry for my late reply.

 

Unfortunately, I can use xsim or irun (Insicive Simulator).

However, I understood your explanation and already tried it.

 

Thanks,

Best regards,

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