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Observer shree9_7
Observer
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Registered: ‎11-15-2019

How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hello Support Team,

I want to make the DisplayPort 1.4 TX subsystem work on the custom design based on the XZCU15EG. But as the example design is based on xzcu102 , I want your suggestions to port this example on XZCU15EG.

As per my initial understanding, DisplayPort 1.4 TX subsystem example is generic and if I modify the DP TX configuration and addresses in xparameters.h file it should work. Is this the correct understanding ?

Thanks in adavance.

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @shree9_7 

It will probably not be as straight forward as just changing the part for the project as the pin mapping will probably change.

You need to do most changes in the vivado design

How are you GT mapped on your board? Did you connected the Video Phy properly for it?

Then in the application you would need to make sure the reference clock is correctly connected to the correct GT input


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
Contributor
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Registered: ‎06-16-2017

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi Shree9_7,

Porting a design from one board to another may not be straight forward.

- Make sure that the GT transceivers are mapped correctly in your board and select the right GT channel location/Bank in the V-PHY IP

- Pay attention to the ref clock for the GT.  You may need to modify the SW to program your clock generation chips if your clocking system is different

- Obviously, you will need to change the XDC file (ZCU102 uses an FMC board, different IO mapping!!)

Good luck!

Hamza.

---

 

Observer shree9_7
Observer
569 Views
Registered: ‎11-15-2019

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @florentw ,

Thanks for yor reply.

We have made the vivado design for it which includes the DP TXSS , VPHY and Timer . Then I modify the example code(mostly the configuration part in xparameters.h file and removed the code for IP's which we are not using) and when I flashed the code on the board and code works fine till XVphy_BufgGtReset() function but it fails at PHY_Configuration_Tx() function(particularly after XVphy_ResetGtPll() function). Definitions for DP14TXSS and VPHY are attached for reference. Please share your thoughts to overcome this issue.

Screenshot from 2019-11-21 11-28-45.png
Screenshot from 2019-11-21 11-25-13.png
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @shree9_7

This is exactly the reason why I am asking how you connected the video phy in vivado. 

What gt reference clock are you using on your board. Is it gtrefclk0, gtrefclk1 or is it coming from a different quad?

The GTs are not locking probably because the reference clock is not selected correctly 

Regards 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
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Registered: ‎11-09-2015

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Also you shouldn't modify the xparameter.h file. It is automatically generated based on the vivado design. 

If it is not correct then the hardware design is not correctly imported 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer shree9_7
Observer
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Registered: ‎11-15-2019

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @florentw ,

The video PHY is connected in a similar way how it is connected in example design. We are using GTREFCLK1 for transmitter and GTREFCLK0 for receiver. In the software also we are selecting the same clocks but still the GT's are not locking properly.

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @shree9_7 

Then what modification did you try to do in the xparameter.h file?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer shree9_7
Observer
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Registered: ‎11-15-2019

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @florentw ,

We don't have some of the IP's which were used in the example design. We have modified the baseaddress, irq numbers for DP, VPHY and Timer and their configuration as posted in the earlier message. Please find the vivado design images attached with this message for your reference.

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Observer shree9_7
Observer
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Registered: ‎11-15-2019

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @florentw ,

As I understand I have to import the hardware to create an application project  in Xilinx SDK and then when we generate BSP/Application project it shows the driver configuration and import example application  option for all the devices which are there in the design. But when I imported our hardware design then Xilinx  SDK has not shown the DPTXSS driver in .mss file and because of that I was not able to import the DPTXSS example.

So, I have created an application project using the example design , changed all addresses and configuration in xparameters.h as per our design and then flashed it to board using our design's .bit file. 

Is there any alternate/better way to compile the example application for custom design?

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Moderator
Moderator
449 Views
Registered: ‎11-09-2015

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @shree9_7 

You should see the DPTXSS in the MSS file if the displayport TX subsystem is in the vivado design. Else there is something wrong with your hdf file. So you should find what is wrong.

You should not change the xparameter.h file manually. This has too much chances of introducting errors


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer shree9_7
Observer
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Registered: ‎11-15-2019

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @florentw,

Did you check the design files and configuration files attached with previous message. Is there anything missing in it ?
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

HI @shree9_7 

Yes I see that there is the DP TX ss in the design. So the issue is with the HDF or the way you import it to SDK.

Can you try to export to a new workspace and see if you can get the DP TX SS in the mss file


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer shree9_7
Observer
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Registered: ‎11-15-2019

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @florentw,
I have tried multiple times by creating new work space but .mss file never shows DPTXSS driver to import the examples.

The hardware specification file was exported from Vivado and imported to Xilinx SDk as per the instruction provided in DPTXSS product guide.
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @shree9_7 

Can you share the hdf file?

Thanks,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer shree9_7
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Registered: ‎11-15-2019

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @florentw ,

Please find the hdf file attached with this message.

Thanks,

shree9_7

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Moderator
Moderator
386 Views
Registered: ‎11-09-2015

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @shree9_7 

Do you have 2 Block designs in your design? If yes this might be the issue. Please do your design in a single block design


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

As per UG1138:

hdf.JPG


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer shree9_7
Observer
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Registered: ‎11-15-2019

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @florentw ,

You were right, our previous design was 2 block design. Now we have changed it to single block design and then we were able to import the example application for DP TXSS. We have removed the unwanted code from application (as we are not using FMC, Test Pattern Generator, Video CRC, IDT 8t49n24x, lmk03318 and Clk_Wiz IP's) and then compiled the application. But we got the same error, application start failing from XVphy_WaitForPmaResetDone() function.

Please find the attached hdf file for your reference.

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @shree9_7 

Can you provide your xdc file?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer shree9_7
Observer
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Registered: ‎11-15-2019

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @florentw ,

Please find the XDC file attached with this message.

 

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

HI @shree9_7 

Thanks I checked your xdc and the connection of the video phy is correct.

Do you have 2 270MHz oscillator output connected to both MGTREFCLK0 and MGTREFCLK1?

Also I checked your design and you made quite a lot of changes compared to the example design. I really recommend you to start with the example design, make it work on your board, then change the design for your custom needs. Else you have to many chances to introduce errors which might take time to debug


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer shree9_7
Observer
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Registered: ‎11-15-2019

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @florentw ,

Thanks for your comments.

I will check with our team on the input frequency on both MGTREFCLK0 and MGTREFCLK1. I will alos check on the possibility of using the example design(but I think it is difficult because example design is using FMC, IDT 8t49n24x , TI LMK03318.. etc. which are not there on our board).

While going through the code I found some register addresses which are used in XDp_TxInitialize() function but I did not info about it in documents. I have attached the images of register addresses and the fucntion which is using it. Can you please point me to the document which are having those register info.

 

Regards,

Shree9_7

Registers.png
Fucntion.png
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

HI @shree9_7 

The registers you are mentionning are part of the DP sub-core. Users are not expected to access them directly, thus they are not documented


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Observer shree9_7
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Registered: ‎11-15-2019

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @florentw ,

Thanks for your input.

I tried the xdp_selftest example on our custom board and iwas also failed. What I understood from code was that it was comparing the XDP_TX_VERSION  and XDP_TX_CORE_ID register default values with values read from board. So what does it mean the values set in the registers are wrong?

If yes, then who is setting those values as I did not see that in code.

Regrads,

Shree9_7

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Registered: ‎11-09-2015

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

HI @shree9_7 

Once again, working at the sub-core level (xdp...) is not supported. Please try with the subsystem selftest DpTxSs_SelfTestExample(u16 DeviceId); if you want to run a selftest example

Regards

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
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Registered: ‎06-16-2017

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @shree9_7 ,

Florent is right. You shouldn't work at the sub-core level. Your problem is definitely somewhere else.

Please, clarify these points:

1- Where are your reference clocks (for GT) coming from?

2- Did you check the ref clock selection in PHY_User_Config_Table[] table? 

The functions that you removed are related to FMC, IDT8t49n24x and TI LMK03318 and are for reference clock generation. So, make sure that your ref clock is connected correctly. If you have a programmable clock generator on your board, make sure it's programmed correctly.

You are having a problem with PHY_Configuration_Tx() function. This function has "PHY_User_Config_Table" as input. Make sure that the table content is consistent with your board.

Good luck!

Hamza

---

Observer shree9_7
Observer
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Registered: ‎11-15-2019

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @florentw , @hamza.bendaoudi ,

You were right, there was ain issue with the external PLL which was connected to reference clock. After programming the PLL to 270 MHz , the code started working. The applications logs are as below

------------------------------------------
DisplayPort TX Subsystem Example Design
(c) 2017 by Xilinx
-------------------------------------------

DisplayPortA��љ�ɵ�initialization done.

INFO:DPTXSS is SST enabled. DPTXSS works only in SST mode.

TX Channel configured for 2byte mode
Reading EDID contents of the DP Monitor..
System capabilities set to: LineRate A, LaneCount 4
Inf0: Setting up of DP TXSS is done.

Training TX with: Link rate A, Lane count 4
.......done !
INFO> Registering Custom Timing Table with 12 entries
- - - - - - - - - - - - - - - - - - - - - - - -
- DisplayPort TX Only Demo Menu -
- Press 'z' to get this main menu at any point -
- - - - - - - - - - - - - - - - - - - - - - - - -
1 - Change Resolution
2 - Change Bits Per Color
3 - Change Number of Lanes, Link Rate
4 - Change Pattern
5 - Display MSA Values for Tx
6 - Change Format
7 - Display Link Configuration Status and user selected resolution, BPC
8 - Display DPCD register Configurations
9 - Read Auxiliary registers
a - Enable/Disable Audio
d - Power Up/Down sink
e - Read EDID from sink
m - Read CRC checker value
z - Display this Menu again
- - - - - - - - - - - - - - - - - - - - - - - - -
You have selected command 7

LINK_BW_SET (0x00100) status in DPCD = A
LANE_COUNT_SET (0x00101) status in DPCD = 4
LANE0_1_STATUS (0x00202) in DPCD = 77
LANE2_3_STATUS (0x00203) in DPCD = 77

SYMBOL_ERROR_COUNT_LANE_0 (0x00210 and 0x00211) Status = 00
SYMBOL_ERROR_COUNT_LANE_1 (0x00212 and 0x00213) Status = 00
SYMBOL_ERROR_COUNT_LANE_2 (0x00214 and 0x00215) Status = 00
SYMBOL_ERROR_COUNT_LANE_3 (0x00216 and 0x00217) Status = 00

Selected Resolution = 3840x2160@30Hz
Selected BPC = 10

You have selected command 8
RX capabilities:
DPCD rev major (0x00000): 1
DPCD rev minor (0x00000): 1
Max link rate (0x00001): 2.70Gbps
Max lane count (0x00002): 4
TPS3 supported (0x00002): N
Enhanced frame support? (0x00002) Y
Max downspread support? (0x00003) N
No AUX handshake required? (0x00003)N
# of receiver ports (0x00004): 1
DP power 5v cap? (0x00004) N
DP power 12v cap? (0x00004) N
DP power 18v cap? (0x00004) N
Downstream ports present? (0x00005) N
Downstreamport0 type (0x00005): DisplayPort
Format conversion block present (0x00005): N
Detailed cap info available? (0x00005) N
Main link ANSI 8b/10b channel coding support? (0x00006) Y
Downstream port count (0x00007): 0
MSA timing parameters ignored? (0x00007) N
OUI supported? (0x00007) Y
Receive port0 local edid present (0x00008) N
Receive port0 associated to preceding port? (0x00008) N
Receive port0 buffer size (0x00009): 32 bytes per lane
Receive port1 local edid present (0x0000A) N
Receive port1 associated to preceding port? (0x0000A) N
Receive port1 buffer size (0x0000B): 32 bytes per lane
I2C speed (0x0000C): No control
EDP alt scrambler reset cap? (0x0000D) N
EDP framing change cap? (0x0000D) N
Training AUX read interval (0x0000E): 100us for CR, 400us for CE
Adapter force load sense cap? (0x0000F) N
Adapter alt i2c pattern cap? (0x0000F) N
Faux cap? (0x00020) N
MSTM cap? (0x00021) N
# of audio eps (0x00022) : 1

You have selected command 5
TX MSA registers:
Clocks, H Total (0x180) : 4400
Clocks, V Total (0x184) : 2250
Polarity (V / H) (0x188) : 3
HSync Width (0x18C) : 88
VSync Width (0x190) : 10
Horz Resolution (0x194) : 3840
Vert Resolution (0x198) : 2160
Horz Start (0x19C) : 384
Vert Start (0x1A0) : 82
Misc0 (0x1A4) : 0x00000040
Misc1 (0x1A8) : 0x00000000
User Pixel Width (0x1B8) : 1
M Vid (0x1AC) : 40351
N Vid (0x1B4) : 32768
Transfer Unit Size (0x1B0) : 64
User Data Count (0x1BC) : 7196
Minimum bytes per TU (0x1C4) : 922337200249503810
Fractional bytes per TU (0x1C8) : 0
Init wait (0x1CC) : 126

Video PHY Config/Status --->
RCS (0x10) = 0x8C000111
PR (0x14) = 0x0
PLS (0x18) = 0x20
TXI (0x1C) = 0x8080808
TXIS(0x20) = 0x7070707
RXI (0x24) = 0x40404040
RXIS(0x28) = 0x4040404
GT DRP Addr (XVPHY_DRP_CPLL_FBDIV) = 0x28, Val = 0x30A
GT DRP Addr (XVPHY_DRP_CPLL_REFCLK_DIV) = 0x2A, Val = 0x840C
GT DRP Addr (XVPHY_DRP_RXOUT_DIV) = 0x63, Val = 0x80C2
GT DRP Addr (XVPHY_DRP_TXOUT_DIV) = 0x7C, Val = 0x2E0
EDID read is :
00 FF FF FF FF FF FF 00 09 E5 25 00 00 00 00 00
0C 19 01 04 A5 1F 11 78 02 B0 90 97 58 54 92 26
1D 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
01 01 01 01 01 01 E8 67 00 D0 F0 70 22 80 30 20
36 00 35 AD 10 00 00 1A 34 D0 00 D0 F0 70 B4 88
30 20 36 00 35 AD 10 00 00 1A 00 00 00 FE 00 48
49 4D 20 41 58 0A 20 20 20 20 20 20 00 00 00 FE
00 48 42 31 34 30 57 58 31 2D 35 30 31 0A 01 8F

FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 7F
EDID read over =======

but still I am not able to see anything on my panel. So, I have below questions :

1) Do you see anything wrong in above logs?

2) Is there anyway that I can programatically create simple pattern(without Test Pattern Generator) and send it to DP?

3) Can I send UHD frame over 2.7Gbps link ? (because 4400 (HTotal) X 2250 (VTotal) X 30 (FPS) X 1 (clock/pixel) X 10 (BPC) = 2.97Gbps

Thanks in advance.

 

Regards,

Shree9_7

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Observer shree9_7
Observer
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Registered: ‎11-15-2019

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @florentw , @hamza.bendaoudi ,

You were right, there was ain issue with the external PLL which was connected to reference clock. After programming the PLL to 270 MHz , the code started working. The applications logs are as below

but still I am not able to see anything on my panel. So, I have below questions :

1) Do you see anything wrong in attached logs?

2) Is there anyway that I can programatically create simple pattern(without Test Pattern Generator) and send it to DP?

3) what is the minimum link bandwidth required to send the UHD at 30FPS?

Thanks in advance.

 

Regards,

Shree9_7

 

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Moderator
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Registered: ‎11-09-2015

Re: How to port the DisplayPort 1.4 TX subsystem example to a custom board

Hi @shree9_7 


@shree9_7 wrote:

 

1) Do you see anything wrong in attached logs?

[Florent] - No, nothing wrong. You might want to check the registers value of the DP core. Also, you might want to make sure you are correctly sending data. You might want to use the pattern generator from the example design

2) Is there anyway that I can programatically create simple pattern(without Test Pattern Generator) and send it to DP?

[Florent] - No, you need to use the pattern generator IP

3) what is the minimum link bandwidth required to send the UHD at 30FPS?

[Florent] - Refer to AR#71499, the computation for the DP BW is mentioned

 


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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