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Explorer
Explorer
842 Views
Registered: ‎10-18-2017

Image Data From UltraScale+ PS to HDMI

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Hello, I am trying to get a feel for the HDMI Transmitter and Video PHY Cores. I would like to create a basic hardware and Linux software platform  where I open a simple image file which I have included in Linux rootfs, like a PNG and continuously stream that image out through HDMI.

I am using the ZCU104 board and have looked at the reVision stack for the board. I am somewhat confused on how the hardware design is actually able to accomplish what it does. It seems to me that the capabilities in that platform would require a direct data link from the Processing System to the Video PHY core through the HDMI Transmitter IP, but I see no such link in the Vivado hardware design. How does the design accomplish this? Does it write directly to the IP registers and how does that affect throughput compared to using Video Direct Memory Access? 

For my design, I was thinking that the way to accomplish this would be to create a VDMA link between the PS and the HDMI Transmitter Core. From the HDMI Transmitter Core, I would then create a link to the Video PHY core then attempt to constrain that to the HDMI port on the ZCU104 board using .xdc files. In the software, I would open the files, then stream the information through the VMDA using a kernel driver. Am I on the right track there or is there a better way?

Thanks.

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Moderator
Moderator
725 Views
Registered: ‎11-09-2015

Re: Image Data From UltraScale+ PS to HDMI

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Hi @johnfrye11,

The m_axi_mm_video port of your Frame Buffer Read is connected to the memory. On the ZCU104, as it is connected to the PS DDR, it is going through the PS.

Yes, m_axis_video is connected to the HDMI TX IP.

If that hardware design makes sense, where does the Frame Buffer Write IP come in?

>It come in only if you have a RX source. In your case you do not need it because you wish to write to memory directly from the PS.

If the design concept above is right, how would Linux coordinate buffering video such that there is simply a kernel buffer that is constantly being read from by the hardware?

> You have to do your application for this.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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5 Replies
Moderator
Moderator
772 Views
Registered: ‎11-09-2015

Re: Image Data From UltraScale+ PS to HDMI

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Hi @johnfrye11,

I believe that the design for ZCU104 the data goes to the VPSS to the frame buffer write and then a frame buffer read to the HDMI IP.

The frame buffer read and write would be like having 2 VDMAs, one for read only and the other write only. For a linux application, you might want to use the video frame buffer IP instead of the VDMA.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Explorer
Explorer
760 Views
Registered: ‎10-18-2017

Re: Image Data From UltraScale+ PS to HDMI

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@florentw

I am trying to visualize the data path from some video buffer in PS (either compressed or uncompressed) to the Video PHY controller. The HDMI TX IP takes an AXI4-Stream Video input if I am not mistaken. If you use the Frame Buffer Read IP, you will have the PS as a slave connected by interconnect to the m_axi_mm_video port of your Frame Buffer Read. You would then connect the m_axis_video to the HDMI TX IP, which is connected to the Video PHY, whose ports are constrained to fit the eval board. Does that sound right?

If that hardware design makes sense, where does the Frame Buffer Write IP come in? If the design concept above is right, how would Linux coordinate buffering video such that there is simply a kernel buffer that is constantly being read from by the hardware?

Thanks

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Moderator
Moderator
726 Views
Registered: ‎11-09-2015

Re: Image Data From UltraScale+ PS to HDMI

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Hi @johnfrye11,

The m_axi_mm_video port of your Frame Buffer Read is connected to the memory. On the ZCU104, as it is connected to the PS DDR, it is going through the PS.

Yes, m_axis_video is connected to the HDMI TX IP.

If that hardware design makes sense, where does the Frame Buffer Write IP come in?

>It come in only if you have a RX source. In your case you do not need it because you wish to write to memory directly from the PS.

If the design concept above is right, how would Linux coordinate buffering video such that there is simply a kernel buffer that is constantly being read from by the hardware?

> You have to do your application for this.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Moderator
Moderator
653 Views
Registered: ‎11-09-2015

Re: Image Data From UltraScale+ PS to HDMI

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HI @johnfrye11,

Do you have any updates on this?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Voyager
Voyager
178 Views
Registered: ‎10-31-2016

Re: Image Data From UltraScale+ PS to HDMI

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hi, 

Coulf you share your application implementation for this ?

Best regards 

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