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Registered: ‎12-25-2018

Implementation of UHD SDI GT and Aurora 64b66b on the same GTH quad of Zynq Ultrascale+ xczu9eg-ffvc900-1-e (Vivado 2018.3)

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Hi,

I would like to know whether it is possible to implement UHD SDI Tx/RX and Aurora 64b66b on the same GTH quad Bank 230 of xczu9eg-ffvc900-1-e ?

I have implemented successfully two UHD SDI Tx/Rx subsystem on Bank 230 at

B230_TX2_P/N,B230_RX2_P/N and B230_TX3_P/N,B230_RX3_P/N. (Use MGTREFCLK1_P/N reference clock)

 

Now I would like to implement Aurora 64b66b on the same quad at B230_TX0_P/N,B230_RX0_P/N. (Use MGTREFCLK0_P/N reference clock)

But after implementation, i get the following errors

ERROR: [Place 30-510] Unroutable Placement! A GTHE_COMMON / GTHE_CHANNEL clock component pair is not placed in a routable site pair. The GTHE_COMMON component can use the dedicated path between the GTHE_COMMON and the GTHE_CHANNEL if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_design_1/design_1_i/aurora_64b66b_0/inst/ultrascale_gt_common_1/design_1_aurora_64b66b_0_0_gt_gthe4_common_wrapper_i/common_inst/gt_qpllclk_quad1_out] >

i_design_1/design_1_i/aurora_64b66b_0/inst/ultrascale_gt_common_1/design_1_aurora_64b66b_0_0_gt_gthe4_common_wrapper_i/common_inst/gthe4_common_gen.GTHE4_COMMON_PRIM_INST (GTHE4_COMMON.QPLL1OUTCLK) is provisionally placed by clockplacer on GTHE4_COMMON_X1Y2
i_design_1/design_1_i/aurora_64b66b_0/inst/design_1_aurora_64b66b_0_0_core_i/design_1_aurora_64b66b_0_0_wrapper_i/design_1_aurora_64b66b_0_0_multi_gt_i/design_1_aurora_64b66b_0_0_gt_i/inst/gen_gtwizard_gthe4_top.design_1_aurora_64b66b_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[27].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.QPLL1CLK) is locked to GTHE4_CHANNEL_X1Y12

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_bufds_gthchannel_intelligent_pin
Status: PASS
Rule Description: A BUFDS driving a GTHChannel must both be placed in the same or adjacent two clock
regions (top/bottom)
i_design_1/design_1_i/aurora_64b66b_0/inst/IBUFDS_GTE4_refclk1 (IBUFDS_GTE4.O) is locked to GTHE4_COMMON_X1Y3
i_design_1/design_1_i/aurora_64b66b_0/inst/design_1_aurora_64b66b_0_0_core_i/design_1_aurora_64b66b_0_0_wrapper_i/design_1_aurora_64b66b_0_0_multi_gt_i/design_1_aurora_64b66b_0_0_gt_i/inst/gen_gtwizard_gthe4_top.design_1_aurora_64b66b_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[27].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.GTREFCLK0) is locked to GTHE4_CHANNEL_X1Y12

Clock Rule: rule_bufds_gthcommon_intelligent_pin
Status: PASS
Rule Description: A BUFDS driving a GTHCommon must both be placed in the same or adjacent two clock
regions (top/bottom)
i_design_1/design_1_i/aurora_64b66b_0/inst/IBUFDS_GTE4_refclk1 (IBUFDS_GTE4.O) is locked to GTHE4_COMMON_X1Y3
i_design_1/design_1_i/aurora_64b66b_0/inst/ultrascale_gt_common_1/design_1_aurora_64b66b_0_0_gt_gthe4_common_wrapper_i/common_inst/gthe4_common_gen.GTHE4_COMMON_PRIM_INST (GTHE4_COMMON.GTREFCLK01) is provisionally placed by clockplacer on GTHE4_COMMON_X1Y2

Clock Rule: rule_gt_bufggt
Status: PASS
Rule Description: A GT driving a BUFG_GT must be placed in the same clock region of the device as the
BUFG
i_design_1/design_1_i/aurora_64b66b_0/inst/design_1_aurora_64b66b_0_0_core_i/design_1_aurora_64b66b_0_0_wrapper_i/design_1_aurora_64b66b_0_0_multi_gt_i/design_1_aurora_64b66b_0_0_gt_i/inst/gen_gtwizard_gthe4_top.design_1_aurora_64b66b_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[27].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.RXOUTCLK) is locked to GTHE4_CHANNEL_X1Y12
i_design_1/design_1_i/aurora_64b66b_0/inst/design_1_aurora_64b66b_0_0_core_i/design_1_aurora_64b66b_0_0_wrapper_i/design_1_aurora_64b66b_0_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst (BUFG_GT.I) is provisionally placed by clockplacer on BUFG_GT_X1Y74

Clock Rule: rule_gthchannel_bufgsync_rx
Status: PASS
Rule Description: A GTHChannel drives a BUFG_GT_SYNC pin must both be in the same clock region and
both have to be in specific sites.
i_design_1/design_1_i/aurora_64b66b_0/inst/design_1_aurora_64b66b_0_0_core_i/design_1_aurora_64b66b_0_0_wrapper_i/design_1_aurora_64b66b_0_0_multi_gt_i/design_1_aurora_64b66b_0_0_gt_i/inst/gen_gtwizard_gthe4_top.design_1_aurora_64b66b_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[27].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.RXOUTCLK) is locked to GTHE4_CHANNEL_X1Y12
i_design_1/design_1_i/aurora_64b66b_0/inst/design_1_aurora_64b66b_0_0_core_i/design_1_aurora_64b66b_0_0_wrapper_i/design_1_aurora_64b66b_0_0_multi_gt_i/design_1_aurora_64b66b_0_0_gt_i/inst/gen_gtwizard_gthe4_top.design_1_aurora_64b66b_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[27].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_1 (BUFG_GT_SYNC.CLK) is provisionally placed by clockplacer on BUFG_GT_SYNC_X1Y48

Clock Rule: rule_gthchannel_bufgsync_tx
Status: PASS
Rule Description: A GTHChannel drives a BUFG_GT_SYNC pin must both be in the same clock region and
both have to be in specific sites.
i_design_1/design_1_i/aurora_64b66b_0/inst/design_1_aurora_64b66b_0_0_core_i/design_1_aurora_64b66b_0_0_wrapper_i/design_1_aurora_64b66b_0_0_multi_gt_i/design_1_aurora_64b66b_0_0_gt_i/inst/gen_gtwizard_gthe4_top.design_1_aurora_64b66b_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[27].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/gthe4_channel_gen.gen_gthe4_channel_inst[0].GTHE4_CHANNEL_PRIM_INST (GTHE4_CHANNEL.TXOUTCLK) is locked to GTHE4_CHANNEL_X1Y12
i_design_1/design_1_i/aurora_64b66b_0/inst/design_1_aurora_64b66b_0_0_core_i/design_1_aurora_64b66b_0_0_wrapper_i/design_1_aurora_64b66b_0_0_multi_gt_i/design_1_aurora_64b66b_0_0_gt_i/inst/gen_gtwizard_gthe4_top.design_1_aurora_64b66b_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[27].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC (BUFG_GT_SYNC.CLK) is provisionally placed by clockplacer on BUFG_GT_SYNC_X1Y46

Clock Rule: rule_bufgsync_bufg_withGTDriver
Status: PASS
Rule Description: A BUFG_GT_SYNC driving a BUFG_GT must be placed in the same clock region of the device
as the BUFG_GT
i_design_1/design_1_i/aurora_64b66b_0/inst/design_1_aurora_64b66b_0_0_core_i/design_1_aurora_64b66b_0_0_wrapper_i/design_1_aurora_64b66b_0_0_multi_gt_i/design_1_aurora_64b66b_0_0_gt_i/inst/gen_gtwizard_gthe4_top.design_1_aurora_64b66b_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[27].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC_1 (BUFG_GT_SYNC.CESYNC) is provisionally placed by clockplacer on BUFG_GT_SYNC_X1Y48
i_design_1/design_1_i/aurora_64b66b_0/inst/design_1_aurora_64b66b_0_0_core_i/design_1_aurora_64b66b_0_0_wrapper_i/design_1_aurora_64b66b_0_0_multi_gt_i/ultrascale_rx_userclk/gen_gtwiz_userclk_rx_main.bufg_gt_usrclk_inst (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X1Y74

Clock Rule: rule_bufgsync_bufg_withGTDriver
Status: PASS
Rule Description: A BUFG_GT_SYNC driving a BUFG_GT must be placed in the same clock region of the device
as the BUFG_GT
i_design_1/design_1_i/aurora_64b66b_0/inst/design_1_aurora_64b66b_0_0_core_i/design_1_aurora_64b66b_0_0_wrapper_i/design_1_aurora_64b66b_0_0_multi_gt_i/design_1_aurora_64b66b_0_0_gt_i/inst/gen_gtwizard_gthe4_top.design_1_aurora_64b66b_0_0_gt_gtwizard_gthe4_inst/gen_gtwizard_gthe4.gen_channel_container[27].gen_enabled_channel.gthe4_channel_wrapper_inst/channel_inst/BUFG_GT_SYNC (BUFG_GT_SYNC.CESYNC) is provisionally placed by clockplacer on BUFG_GT_SYNC_X1Y46
i_design_1/design_1_i/aurora_64b66b_0/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk2_inst (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X1Y72
i_design_1/design_1_i/aurora_64b66b_0/inst/clock_module_i/ultrascale_tx_userclk_1/gen_gtwiz_userclk_tx_main.bufg_gt_usrclk_inst (BUFG_GT.CE) is provisionally placed by clockplacer on BUFG_GT_X1Y73

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 167fc8be6

Time (s): cpu = 00:01:51 ; elapsed = 00:01:37 . Memory (MB): peak = 5228.074 ; gain = 954.270
Phase 1 Placer Initialization | Checksum: 167fc8be6

Time (s): cpu = 00:01:51 ; elapsed = 00:01:37 . Memory (MB): peak = 5228.074 ; gain = 954.270
ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer failed'
Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
Ending Placer Task | Checksum: 128892a1b

Time (s): cpu = 00:01:51 ; elapsed = 00:01:37 . Memory (MB): peak = 5228.074 ; gain = 954.270
INFO: [Common 17-83] Releasing license: Implementation
243 Infos, 133 Warnings, 1 Critical Warnings and 3 Errors encountered.
place_design failed
ERROR: [Common 17-69] Command failed: Placer could not place all instances
INFO: [Common 17-206] Exiting Vivado at Tue Aug 20 14:27:07 2019...

Regards

YE

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Xilinx Employee
Xilinx Employee
354 Views
Registered: ‎11-29-2007

Re: Implementation of UHD SDI GT and Aurora 64b66b on the same GTH quad of Zynq Ultrascale+ xczu9eg-ffvc900-1-e (Vivado 2018.3)

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Hello,

generating the Aurora 64/66 IP without the GT should allow more flexibility. I assume that the QPLL frequency you will use will be the same or multiple for UHD SDI and Aurora applications.

Image 1566391922.png

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3 Replies
Highlighted
Xilinx Employee
Xilinx Employee
355 Views
Registered: ‎11-29-2007

Re: Implementation of UHD SDI GT and Aurora 64b66b on the same GTH quad of Zynq Ultrascale+ xczu9eg-ffvc900-1-e (Vivado 2018.3)

Jump to solution

Hello,

generating the Aurora 64/66 IP without the GT should allow more flexibility. I assume that the QPLL frequency you will use will be the same or multiple for UHD SDI and Aurora applications.

Image 1566391922.png

View solution in original post

Moderator
Moderator
315 Views
Registered: ‎11-21-2018

Re: Implementation of UHD SDI GT and Aurora 64b66b on the same GTH quad of Zynq Ultrascale+ xczu9eg-ffvc900-1-e (Vivado 2018.3)

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Hi yan-eng.ang@leica-microsystems.com 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

 

If this is not solved/answered, please reply in the topic giving more information on your current status.

 

Thanks and Regards,

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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307 Views
Registered: ‎12-25-2018

Re: Implementation of UHD SDI GT and Aurora 64b66b on the same GTH quad of Zynq Ultrascale+ xczu9eg-ffvc900-1-e (Vivado 2018.3)

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Hi Aoife,

We will implement Aurora and SDI protocol on different GTH quad for now. I think significant effort is needed if the GT is outside the IP.

Thanks.

Regards

YE

 

 

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