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Adventurer
Adventurer
7,175 Views
Registered: ‎04-07-2011

Implementing a floating Point Multiplier using HDL Coder and Simulink

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Hi All

 

I am not much aware of the HDL Coder. i would be in fact using it for the first time now. I need to implement a floating point multiplier which would accept a 14 bit value (std_logic_vector) and a  coefficient (floating point). Is there anyone who has done something on similar lines? If yes please reply, I needed to clarify few points.

 

Looking forward to replies.

 

Akanksha

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Xilinx Employee
Xilinx Employee
7,459 Views
Registered: ‎11-28-2007

Re: Implementing a floating Point Multiplier using HDL Coder and Simulink

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HLS will generate the CoreGen/Vivado floating point cores behind the scene, so the performance will be the same as far as floating point operations are concerned. The nice thing about HLS is that you can easily explore different architectures (serial, parallel, or semi-parallel to meet your requirements.

 

Yes, you can pick any c function in your c code to be the top level for C synthesis. It has to be a function though, it can't be just section of a C code within a fucntion.

@lamiastella wrote:

Hi,

Which of the mentioned tools are better for multiplitying two floating point array? If I use CoreGeneratore FPU should I instantiate it according to array length? Don't we have a type named something FLOAT_ARRAY in XilinX? And Is it efficient to implement array of floating point multiplication in FPGA?

 

P.S.: Can I run my C code in Vivado HLS and select only a specific function in order to be converted to HDL and run in FPGA? The tutorials I was following were doing the conversion for the whole C code.

 

Best regards,

Mona Jalal.




Cheers,
Jim
7 Replies
Xilinx Employee
Xilinx Employee
7,168 Views
Registered: ‎08-02-2011

Re: Implementing a floating Point Multiplier using HDL Coder and Simulink

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Hello,

 

Well HDL Coder is a mathworks tool, so I would start there.

 

If you are looking for a Xilinx solution, you can use sysgen for floating point processing. Or you can use coregen to generate floating point cores which can be used in your design.

www.xilinx.com
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Adventurer
Adventurer
7,107 Views
Registered: ‎04-07-2011

Re: Implementing a floating Point Multiplier using HDL Coder and Simulink

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Hi Bweic

 

Thanks for the reply.  Yes I would be using Floating point core in my design. However, I had a  few doubts while going through its datasheet. If you could please help me in resolving them.

 

1. If floating point core is already available , under what circumstances does using an Auto ESL (now bundled with Vivado) or using HDL Coder become necessary.  Is it just to facilitate a Matalab to HDL /C to HDL conversion?

 

2. I could not follow the Customisation options mentioned in the IP Core GUI for floating point operator namely:

Medium Usage

Full Usage

Max Usage and the latency clocks derived for them.

 

3. On reducing the latency clock,other than the increase in the hardware resources, is there any difference in terms of speed or optimisation too ? What should be the criteria on deciding the latency? Or is it purely in the requirement for the output?

 

4. For Floatng point multiplication using this IP Core, is it possible to use two different inputs  - a 14 bit digital input (converted to 32 bit fixed point) and a 32 bit floating point value to yield a 32 bit floating point output?

I mean, is it possible to send mixed set of inputs to the CORE. If not then would it involve using one instance of the IP core for fixed to floating point conversion before proceeding with the floating point multiplication?

 

Look forward to your reply.

 

akanksha

 

 

 

 

 

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Xilinx Employee
Xilinx Employee
7,099 Views
Registered: ‎08-02-2011

Re: Implementing a floating Point Multiplier using HDL Coder and Simulink

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Hello,

 

Ah okay.

 

1. They are different tools for different purposes. If you are more comfortable with model-based design and/or simulink, use sysgen. If you are more comfortable with C coding, use Vivado HLS (previously AutoESL). If you are more comfortable using HDL, use the normal ISE/Planahead/Vivado flows.

 

2. This is answered on page 72 of the product guide for the Floating-Point Operators core (Table 5-3 on PG060 from July 25, 2012). It is related to DSP slice utilization.

 

3. Changing the latency will affect the amount of pipelining within the core and will most likely affect your speed. This is discussed in the 'Performance' section of the above mentioned PG. Deciding how much latency you need will depend on the design. It is the classic tradeoff between latency and throughput (registers are basically free in an FPGA from an area standpoint). In short, the more throughput/speed you need, the more pipelining registers you should add. But this increases your latency, which also must meet your design criteria.

 

4. No, it is not possible to used mixed precision inputs like this. You must do fixed-to-float conversion, as you mentioned.

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Adventurer
Adventurer
7,084 Views
Registered: ‎04-07-2011

Re: Implementing a floating Point Multiplier using HDL Coder and Simulink

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Hey Thanks for replying.

 

I did go through the Product guide. However, my query still persists.

In DSP Slice max usage, what does DSP Multiplier body and rounder actually mean ? How is it different from tht in Full usage.

In max, 5 DSP48A slices are used and in full it is 4.  then why is the latency in Max(10) lower tahn that in full(11)?

 

What should be the criteria to go for these usage?

 

Sorry for bothering you again.

 

akanksha

 

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Xilinx Employee
Xilinx Employee
7,079 Views
Registered: ‎08-02-2011

Re: Implementing a floating Point Multiplier using HDL Coder and Simulink

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Multiplier body means that the DSP slice is used for implementing the multiplication operation. Rounder means an additional DSP slice will be used for the rounding operation (as opposed to logic).

 

In short, it is generally best to use DSP slices if you have them avaialable. They are free, faster, and lower power. If you are running low on them, you can go back and balance speed with area to use DSP slices at the bottlenecks of the design and use fabric where you don't need the speed.

www.xilinx.com
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Visitor lamiastella
Visitor
6,338 Views
Registered: ‎11-28-2012

Re: Implementing a floating Point Multiplier using HDL Coder and Simulink

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Hi,

Which of the mentioned tools are better for multiplitying two floating point array? If I use CoreGeneratore FPU should I instantiate it according to array length? Don't we have a type named something FLOAT_ARRAY in XilinX? And Is it efficient to implement array of floating point multiplication in FPGA?

 

P.S.: Can I run my C code in Vivado HLS and select only a specific function in order to be converted to HDL and run in FPGA? The tutorials I was following were doing the conversion for the whole C code.

 

Best regards,

Mona Jalal.

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Xilinx Employee
Xilinx Employee
7,460 Views
Registered: ‎11-28-2007

Re: Implementing a floating Point Multiplier using HDL Coder and Simulink

Jump to solution

HLS will generate the CoreGen/Vivado floating point cores behind the scene, so the performance will be the same as far as floating point operations are concerned. The nice thing about HLS is that you can easily explore different architectures (serial, parallel, or semi-parallel to meet your requirements.

 

Yes, you can pick any c function in your c code to be the top level for C synthesis. It has to be a function though, it can't be just section of a C code within a fucntion.

@lamiastella wrote:

Hi,

Which of the mentioned tools are better for multiplitying two floating point array? If I use CoreGeneratore FPU should I instantiate it according to array length? Don't we have a type named something FLOAT_ARRAY in XilinX? And Is it efficient to implement array of floating point multiplication in FPGA?

 

P.S.: Can I run my C code in Vivado HLS and select only a specific function in order to be converted to HDL and run in FPGA? The tutorials I was following were doing the conversion for the whole C code.

 

Best regards,

Mona Jalal.




Cheers,
Jim