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Registered: ‎01-21-2019

Interlaced Video - VMDA and VTG Configuration

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We have a system that is working pretty good with progressive video signals. However, when an interlaced signal is introduced into the system we get a common situation where Frame Fields are not aligned with the frame data stream. The result is odd frames displayed where even frames should be and even frames displayed when odd frames should be displayed.

Here is our general diagram below.

General Systems Flow, V1.0.jpg

 

 

The problem seems to be that the VDMA gets backed up, at somepoint, and displays the same buffer over again. When this happens the VTG keeps sending out the alternating field codes (0/1) but when the VDMA repeats a buffer then the field and frame get out of sync. The image looks pretty bad until the VDMA gets out of sync again and everything looks good again.  We think the timing on the S2MM side and the MM2S side is such that after about 45 seconds the buffer threatens an overrun and the VDMA repeats a buffer to realign everything again.  That seems normal.

However, since the VDMA doesn't pay attention to Field codes, how do we ensure the Field code matches the buffer being sent out of the VDMA?  Is there something that aligns the VDMA with the VTG and/or vice versa?

What is the standard practice these days?

Thank you.

Phil

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Moderator
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291 Views
Registered: ‎11-09-2015

Re: Interlaced Video - VDMA and VTG Configuration

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Hi phil@pswitchers.com,

Not sure how interlaced data can be handled. What I would do is to you multiple VDMAs: 2 for write and 2 for read (with 2 frame buffer each). Then you can do some logic to write/read from a specific VDMA depending on if you are on an odd or even field.

However, there might be a better solution, but I cannot see it for the moment.

Please share if you have a better idea

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
10 Replies
Moderator
Moderator
292 Views
Registered: ‎11-09-2015

Re: Interlaced Video - VDMA and VTG Configuration

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Hi phil@pswitchers.com,

Not sure how interlaced data can be handled. What I would do is to you multiple VDMAs: 2 for write and 2 for read (with 2 frame buffer each). Then you can do some logic to write/read from a specific VDMA depending on if you are on an odd or even field.

However, there might be a better solution, but I cannot see it for the moment.

Please share if you have a better idea

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Adventurer
Adventurer
254 Views
Registered: ‎07-18-2011

Re: Interlaced Video - VDMA and VTG Configuration

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phil@pswitchers.com

Is there any reason you can't add a deinterlacer prior to the VDMA input, so you don't have to worry about frame drop/repeats in the frame synchronization? 

Interlaced video is always a pain to deal with, particularly if you are doing any overlays or character generation.

If you need to output interlaced video, you can always add an interlacer on the output side.  This can easily be done by vertically filtering using three line buffers weighted at 0.25, 0.5, 0.25, averaging up in odd fields and down in even fields.   Alternately, you could implement simple scan-line decimation, but 3-line vertical filtering looks better.

 

 

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Registered: ‎01-21-2019

Re: Interlaced Video - VDMA and VTG Configuration

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Realken,

Good idea. Thank you for your suggestion.

We could add a deinterlacer prior to the VDMA but we are lacking resources in this current size of FPGA. We are modifying a couple of our prototyope boards with larger FPGAs just to do exactly as you suggest.  Our goal has been that what comes in is what goes out but interlaced signals have turned into a big problem. One would think that interlaced video is a problem that would have been solved many times over in the past.

I am going to run your idea of vertical weighting by our team and see if this will solve our problem without the jump in FPGA size.

Thank you again!

Phil

 

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Registered: ‎07-18-2011

Re: Interlaced Video - VDMA and VTG Configuration

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phil@pswitchers.com

Limited resources are no fun, I really envy these guys who get to use Kintexes and Virtexes.

Back in the Dark Ages when I designed NTSC/PAL broadcast video frame syncs and TBCs in hardware instead of these wonderful FPGAs, I would insert the field ID on the lsb of the first pixel in each field on the write side of the memory, then recover it on the read side of the memory.   This would allow me to determine which field was being read out and process the video accordingly.

You might be able to make use of something like this to keep your fields correct when dropping/repeating a field in interlaced mode. 

 

 

 

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Registered: ‎01-21-2019

Re: Interlaced Video - VDMA and VTG Configuration

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Reaiken,

We are currently handling the Field ID "flag" exactly as you have stated.

We are embedding a number of flags in the LSB of the first pixel of each frame for exactly the same purpose. The problem is that the VTG is what we are using for timing and it has it's own Field ID it generates. Plus, the VSync is offset when Field ID = 1.  It would be nice if we could feed our Field ID flag into the VTG and it would resync/reset the timing parameters using the new Field ID.

If we were able to influence the VTG I'm not sure how a display would react to two consecutive Frame ID's when the VDMA handles frame syncronization.  I suppose that problem is going to occur one way or another regardless.

Glad to hear we weren't the only ones thinking this way!

Regards,

Phil

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Registered: ‎07-18-2011

Re: Interlaced Video - VDMA and VTG Configuration

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phil@pswitchers.com

You can't use the recovered field ID to change the outgoing field ID on the fly, because, as you have correctly surmised, it wouldn't match the VTC.  The output field ID sequence has to remain constant, locked to the VTC.

You may be able to accomplish what you want by using the embedded field ID to detect when the read field ID doesn't match the VTC field ID, then effectively shift the video up or down by one line (by using a switchable line delay) to make an odd field into an even field, or vice-versa.  Your video is still coming out in a correct time sequence, the shifted output interlaced vertical sync is just making the monitor display the video fields in the incorrect vertical position.

This is similar to the way you handle a field freeze of interlaced video, where you have to generate a two-field frame sequence from a single stationary field read.  If you try to do a frame freeze on live motion interlaced video, you will get a frozen image that jumps back and forth, so you normally just do a field freeze and line-interpolate to make the other field.

 

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157 Views
Registered: ‎11-09-2015

Re: Interlaced Video - VDMA and VTG Configuration

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Hi phil@pswitchers.com ,

Do you have any updates on this? Were the replies enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Registered: ‎01-21-2019

Re: Interlaced Video - VDMA and VTG Configuration

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We are attempting to use two VDMAs. One to handle Field 0 and one to handle Field 1. Then, we use the timing data from the VTG to tell us what buffer to pull from when sending data to the Video Output block. It's not as clean as we would like to see but we cannot see a better option, at this point.

I am hopeful that Xilinx modifies their VDMA code at some point and adds interlaced signals to their list of support video structures/formats.

Shall we close this discussion or leave it open until we resolve the problem completely? 

Regards,

Phil

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Registered: ‎11-09-2015

Re: Interlaced Video - VDMA and VTG Configuration

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Hi phil@pswitchers.com ,

Just to set the expectation: I do not think the AXI VDMA IP will be changed.

You might want to look at the frame buffer read and write. This is another solution which should support interlaced. This is because this is interrupt driver, thus you can have a better control on which buffer you write into.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Registered: ‎01-21-2019

Re: Interlaced Video - VDMA and VTG Configuration

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Thank you.  Good to know.

I will close this conversation.

You have been awesome!

Phil