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Anonymous
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Interlaced video support for these IP cores in Vivado 2015.2

In order to interface PAL encoder to decoder, we are using VTC to generate hsync and vsync signals (as input to Encoder). I understand that the sync signals which come from decoder will be lost in the video pipeline. Hence, I want to know what IP cores (among the ones listed below) support interlaced video. I use Vivado 15.2.

 

Video In to AXI4-Stream (3.0)

VDMA (6.2)

Video Timing controller (6.1)

AXI4-Stream In to Video (3.0)

 

Are there any issues in the above mentioned cores which were noted and resolved in later versions? (For example in this post)

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Mentor
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Registered: ‎06-16-2013

Re: Interlaced video support for these IP cores in Vivado 2015.2

Hi meghanadk

 

I don't have best answer for your question.

But I recommend to refer the following URL.

It's little different for what you want. But it's very helpful for you.

 

http://www.wiki.xilinx.com/Zynq+Base+TRD+2015.2

 

This design is for HDMI input/output and uses YUV4:2:2 signal with the following IPs.

 

Video In to AXI4-Stream (3.0)

VDMA (6.2)

Video Timing controller (6.1)

AXI4-Stream In to Video (3.0)

 

BTW, I have a question about how to deal with interlace ?

If PAL encoder accept pseud field signal, I think you generate toggled field signal.

My country is NTSC region. But I'm interesting about it.

 

Thank you.

Best regards,

 

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