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Contributor
Contributor
943 Views
Registered: ‎04-10-2018

LPS time in CSI-2 Tx IP core

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Hello guys,

The MIPI protocol has a blanking state that is the Low Power State (LPS).

 

In the CSI-2 Tx IP core, what is the defined value of the LPS? How can I control it?

 

I'm creating an application which will have a large frame rate (arround 2000 fps). Recently, I create a frame rate near of 1600 fps, but the LPS value prevents me from reaching the desired frame rate. The LPS has a duration arround 1.22 us for a line rate of 1250 Mbps.

 

Studing the MIPI D-PHY user guide, I found the table 2-1 which shows the latency for D-PHY Core Configurations. For my kintex-7 FPGA, I'm using 4 lanes and a line rate of 1250 Mbps. From the equation:

 

LPS_time = (Latency)*4/((Line_rate)/8) = 48*4/(1250/8) = 1.2288 us

 

This behavior remains the same for other configurations using 4 lanes. I thought the "4" factor in the equation above was the value of the lanes which I'm using, but for two lanes, the LPS value was the same.

 

What is the relationship between the D-PHY latency and the LPS time? How can I change this value?

 

I'm using a AXI4-Streaming interface, and the image is a RAW12 512x256 image.

 

Thank you all for help.

 

Regards

 

Marcos

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Xilinx Employee
Xilinx Employee
904 Views
Registered: ‎03-30-2016

Re: LPS time in CSI-2 Tx IP core

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Hello Marcos @marcos.bissiano
I hope you are doing fine.

 

Okay I can understand your problem here.

>In the CSI-2 Tx IP core, what is the defined value of the LPS? How can I control it?

 

1. CSI-2 TX IP will exit LPS if you start to transmit HS data by asserting s_axis_tvalid=1.
2. CSI-2 TX IP will enter LPS after you assert s_axis_tlast. (triggered when you send the last pixel)
3. When you are using CSI-2 TX IP, you can start the next HS transfer by asserting s_axis_tvalid, right after the assertion of s_axis_tlast, since in this IP we have line buffer.
But from MIPI D-PHY perspective, we have to send HS-TRAIL, HS-SKIP, LP-11, LP-01, LP-00, HS-SETTLE before sending the next HS-transfer. This is the main overhead/limitation with MIPI D-PHY ver1.1 spec. Especially min LPX value == 50ns as stated will probably give a big overhead if you are using high framerate. As you can see that half of the latency value is LPX period which is already the minimal value, we cannot decrease this value anymore. (without violating MIPI spec)

 

Some suggestions :

(a) Are you using UltraScale+ device, with speed grade:-2  ? If yes I would suggest you to increase the line rate to the max 1500Mbps.
(b) Are you using non-continuous clock mode ? I would try Continuous clock-mode since it will reduce LPS time, because your clock lane can stay on HS state.

 

Best regards
Leo

-- MIPI CSI-2 rev2.0 can support EPD (Efficient Packet Delimiter), which might solve your problem. but unfortunately it is not supported on ver1.1 spec.
-- BTW, your calculation is not correct. Lane number setting does not affect latency value.

XF_MARCOS_LPS_LPX.png
7 Replies
Xilinx Employee
Xilinx Employee
905 Views
Registered: ‎03-30-2016

Re: LPS time in CSI-2 Tx IP core

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Hello Marcos @marcos.bissiano
I hope you are doing fine.

 

Okay I can understand your problem here.

>In the CSI-2 Tx IP core, what is the defined value of the LPS? How can I control it?

 

1. CSI-2 TX IP will exit LPS if you start to transmit HS data by asserting s_axis_tvalid=1.
2. CSI-2 TX IP will enter LPS after you assert s_axis_tlast. (triggered when you send the last pixel)
3. When you are using CSI-2 TX IP, you can start the next HS transfer by asserting s_axis_tvalid, right after the assertion of s_axis_tlast, since in this IP we have line buffer.
But from MIPI D-PHY perspective, we have to send HS-TRAIL, HS-SKIP, LP-11, LP-01, LP-00, HS-SETTLE before sending the next HS-transfer. This is the main overhead/limitation with MIPI D-PHY ver1.1 spec. Especially min LPX value == 50ns as stated will probably give a big overhead if you are using high framerate. As you can see that half of the latency value is LPX period which is already the minimal value, we cannot decrease this value anymore. (without violating MIPI spec)

 

Some suggestions :

(a) Are you using UltraScale+ device, with speed grade:-2  ? If yes I would suggest you to increase the line rate to the max 1500Mbps.
(b) Are you using non-continuous clock mode ? I would try Continuous clock-mode since it will reduce LPS time, because your clock lane can stay on HS state.

 

Best regards
Leo

-- MIPI CSI-2 rev2.0 can support EPD (Efficient Packet Delimiter), which might solve your problem. but unfortunately it is not supported on ver1.1 spec.
-- BTW, your calculation is not correct. Lane number setting does not affect latency value.

XF_MARCOS_LPS_LPX.png
Contributor
Contributor
885 Views
Registered: ‎04-10-2018

Re: LPS time in CSI-2 Tx IP core

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Hello Leo @karnanl, thank you for answer

(a) Are you using UltraScale+ device, with speed grade:-2  ? If yes I would suggest you to increase the line rate to the max 1500Mbps.
No, I'm using a Kintex-7 xc7k410t, which the line rate maximun is 1250.

(b) Are you using non-continuous clock mode ? I would try Continuous clock-mode since it will reduce LPS time, because your clock lane can stay on HS state.
Yes, I was using a non-continuous clock mode. I change it to a continuous clock-mode, but the LPS still having the same time.
I change the active line to 1024 pixels, and in this configuration, the LPS reduced in 4 times when I use the continuous clock mode. Does this result make sense?

thank you

regards

Marcos

Xilinx Employee
Xilinx Employee
841 Views
Registered: ‎03-30-2016

Re: LPS time in CSI-2 Tx IP core

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Hello Marcos @marcos.bissiano

 

>No, I'm using a Kintex-7 xc7k410t, which the line rate maximun is 1250.

 

Okay, I understand your circumstance.

 

>Yes, I was using a non-continuous clock mode. I change it to a continuous clock-mode,
>but the LPS still having the same time. I change the active line to 1024 pixels, and in this configuration,

>the LPS reduced in 4 times when I use the continuous clock mode. Does this result make sense?

 

This is not expected. Please let me confirm if my understanding is correct.

 

1. Regarding your experiment. Could you please confirm if my understanding is correct ?

You are using the same Line-rate (which is 1250Mbps).
(a) Non-continuous clock

     When you changed MIPI CSI-2 TX input data from (active lane=512) to (active lane=1024). No change on LPS timing.

(b) Continuous clock

     When you changed MIPI CSI-2 TX input data from (active lane=512) to (active lane=1024). LPS timing changes.

 

2. Did you try to re-initialize MIPI CSI-2 TX SS after you changed the Continuous/Non-continuous clock mode ?

3. How do you find out that your LPS time is still the same ? (Do you have any scope-shot to share ?)

 

Thanks & regards

Leo

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Moderator
Moderator
768 Views
Registered: ‎11-09-2015

Re: LPS time in CSI-2 Tx IP core

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Hello @marcos.bissiano,

 

Were the replies from @karnanl enough for you?

 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Contributor
Contributor
578 Views
Registered: ‎04-10-2018

Re: LPS time in CSI-2 Tx IP core

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Hello Leo, @karnanl

I'm sorry for the delay for answering. My team was concentrated in another task and I could not answer before.

Btw, I design a simple TPG/CSI project to test my doubt, and create the follow table:

table.jpeg

tpg_to_csi2.jpeg

The waveform is in respect of the last test.

As expected, the continuous/non-continuous signal really improve the frame rate, reducing the LPS time. My unique misunderstand is what are causing this minimum LPS time. The yellow highlighted collumns are a comparison for different line rates, and the LPS has the same time, on the other hand the frame rate are improved.

My doubt was in respect to the relation betweem LPS time and line rate, what could makes me more able to calculate the optimal values to my project.

thank you all for help.

Regards,

Marcos

tpg_to_csi2.jpeg
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Xilinx Employee
Xilinx Employee
571 Views
Registered: ‎03-30-2016

Re: LPS time in CSI-2 Tx IP core

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Hello Marcos @marcos.bissiano

Thank you for sharing your progress !
Could you please kindly marked this thread as Solved thread ? ( so other Forum users can learn from your experience too )

Thanks & regards
Leo

Contributor
Contributor
557 Views
Registered: ‎04-10-2018

Re: LPS time in CSI-2 Tx IP core

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Hello @karnanl and @florentw

Thank you for all help.

I took the liberty to share an image of my block diagram with a minimal image MIPI generator, if this may help:

bd_diagram.jpeg

Best Regards

Marcos