06-13-2018 04:57 AM
I am attempting a loop back simulation with CSI TX and RX in vivado 2017.4
Problem : No Video out from CSI Rx
1. Generated TX & RX cores with following options
- 2 Lanes
- native video interface in TX
- input pixels per beat 1
- line buffer depth 2048
- CRC disablesd
- Line rate 1000 Mbps
- AXI4 Lite interface enabled
- include shared logic in core
- Calibration Mode - None for Rx
- Rx Idelay Tap value - 1
2. Connected the PHY line of Tx and Rx
3. Followed the configuration sequence attached
1. Both the TX and RX DPHY gives init_done signal. Confirmed by register read also.
2. Tx PHY activities happens after the Init Done.
3. No activities on the video signals at the RX out.
The waveform is attached
Can you please help me to find out whether I missed something.?
06-13-2018 07:16 PM
Your D-PHY RX rxbyteclkhs is toggling, so clock lane is working correctly.
1. Could you please check if MIPI D-PHY RX PPI interface is toggling correctly ?
( Signal are listed in PG202 Table 2-10, 2-11)
2. If D-PHY RX PPI I/F is not toggling at all, could you please
- Check if the data serial lanes are correctly connected ?
- Try to test Calibration None --> Fixed ?
06-14-2018 01:32 AM
Thank you. I Tried your suggestions.
1. DPHY RX PPI Interface is not toggling.
2. The serial lanes are connected correctly.
Tried with calibration FIXED. But no signal activities are observed.
06-14-2018 08:10 AM
One observation on the RX system reset, It is on the 'High' state and did not come low, Does this give us any clue..? Please See the waveform attached.
06-18-2018 03:20 AM
According to your sim waveform init_done is not even asserted yet. Your RX IP will not work.
1. Do you supply 200MHz free run clock to the IP ?
2. Is system_reset_out asserted high all the time ?
3. Could you please check your register
(a). core enable =1
(b). srst =0
06-18-2018 03:29 AM
The Init_done is going high.(Please see the waveform in first replay reply).
1. Yes. The 200MHz clk is running uninterrupted.
2. The system reset_out remains high all the time after the initial toggling.
3. core enable =1, srst =0 Confirmed through register read.
06-18-2018 10:48 PM
Hello Jobin @jobincyriac
1. Your waveform shows that core_rst is low, so this is okay.
2. I am wondering if you are include IDELAYCTRL in your design.
7 series needs IDELAYCTRL to be instantiated if you are using IDELAY2 primitives.
Could you please confirm that ?
If your design has already IDELAYCTRL instantiated but sim does not work,
I would like to check your Vivado sim testbench+environment.