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MIPI CSI-2 Rx simulation Vivado 2017.4

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Visitor
Posts: 9
Registered: ‎06-11-2018
Accepted Solution

MIPI CSI-2 Rx simulation Vivado 2017.4

Hi,

 

I am attempting a loop back simulation with CSI TX and RX in vivado 2017.4 

Problem  : No Video out from CSI Rx 

 

Steps followed

1. Generated TX & RX cores with following options

- 2 Lanes

- native video interface in TX

- input pixels per beat 1

- line buffer depth 2048

- CRC disablesd

- Line rate 1000 Mbps

- AXI4 Lite interface enabled

- include shared logic in core

- Calibration Mode - None for Rx

- Rx Idelay Tap value - 1

 

2. Connected the PHY line of Tx and Rx

3. Followed the configuration sequence attached

 

Observations: 

1. Both the TX and RX DPHY gives init_done signal. Confirmed by register read also.

2. Tx PHY activities happens after the Init Done.

3. No activities on the video signals at the RX out.

 

The waveform is attached

 

Can you please help me to find out whether I missed something.?

 

Thank You,

Jobin  

 

 


Accepted Solutions
Xilinx Employee
Posts: 168
Registered: ‎03-30-2016

Re: MIPI CSI-2 Rx simulation Vivado 2017.4

[ Edited ]

Hello Jobin @jobincyriac

 

Thank you very much for sharing your simulation testbench, I have a look on it.

 

1. It seems you are using Native Interface for CSI-2 TX.

2. Please check PG260 Appendix B, Figure B-3 for CSI-2 TX Native interface sample waveform.

3. As stated in PG260, vid_hsync and vid_vsync is High-active signal. Please fix the testbench.

4. When vid_vsync is asserted , MIPI CSI-2 TX will send packet for Frame-Start

5. vid_hsync should keep high, when you are sending your video data.

6. Please set at least 1 period of s_axis_aclk for HBP/HFP. ( we will update PG260 for future release )

7. Data type for RAW8 is 0x2A, you set it as 0x28 ( which mean RAW6) .

 

Please modify your testbench so MIPI CSI-2 TX can send data correctly,

we can discuss the RX part if you have a further problem.

 

Best regards

Leo

View solution in original post

CSI2_DATA_TYPE.png

All Replies
Xilinx Employee
Posts: 168
Registered: ‎03-30-2016

Re: MIPI CSI-2 Rx simulation Vivado 2017.4

Hello @jobincyriac

 

Your D-PHY RX rxbyteclkhs is toggling, so clock lane is working correctly.

1. Could you please check if MIPI D-PHY RX PPI interface is toggling correctly ?
    ( Signal are listed in PG202 Table 2-10, 2-11)

2. If D-PHY RX PPI I/F is not toggling at all, could you please 

    - Check if the data serial lanes are correctly connected ?

    - Try to test Calibration None --> Fixed ?

 

Best regards

Leo

Visitor
Posts: 9
Registered: ‎06-11-2018

Re: MIPI CSI-2 Rx simulation Vivado 2017.4

Hello @karnanl

 

Thank you. I Tried your suggestions.

1. DPHY RX PPI Interface is not toggling. 

2. The serial lanes are connected correctly.

     Tried with calibration FIXED. But no signal activities are observed.

 

Regards,

Jobin

     

 

 

wf3.JPG
Visitor
Posts: 9
Registered: ‎06-11-2018

Re: MIPI CSI-2 Rx simulation Vivado 2017.4

Hello @karnanl,

 

One observation on the RX system reset, It is on the 'High' state and did not come low, Does this give us any clue..? Please See the waveform attached.

 

Regards,

Jobin

wf4.JPG
Xilinx Employee
Posts: 168
Registered: ‎03-30-2016

Re: MIPI CSI-2 Rx simulation Vivado 2017.4

Hello @jobincyriac

 

According to your sim waveform init_done is not even asserted yet. Your RX IP will not work.

1. Do you supply 200MHz free run clock to the IP ?

2. Is system_reset_out asserted high all the time ?

3. Could you please check your register

    (a). core enable =1

    (b). srst =0

 

Best regards

Leo

 

Visitor
Posts: 9
Registered: ‎06-11-2018

Re: MIPI CSI-2 Rx simulation Vivado 2017.4

Hello @karnanl,

 

The Init_done is going high.(Please see the waveform in first replay reply).

1. Yes. The 200MHz clk is running uninterrupted.

2. The system reset_out remains high all the time after the initial toggling.

3.  core enable =1, srst =0 Confirmed through register read.

 

regards,

Jobin

Xilinx Employee
Posts: 168
Registered: ‎03-30-2016

Re: MIPI CSI-2 Rx simulation Vivado 2017.4

Hello Jobin  @jobincyriac

 

1. Your waveform shows that core_rst is low, so this is okay. 

2. I am wondering if you are include IDELAYCTRL in your design.

    7 series needs IDELAYCTRL to be instantiated if you are using IDELAY2 primitives.

    Could you please confirm that ?

 

If your design has already IDELAYCTRL instantiated but sim does not work, 

I would like to check your Vivado sim testbench+environment. 

 

Best regards

Leo

 

Xilinx Employee
Posts: 168
Registered: ‎03-30-2016

Re: MIPI CSI-2 Rx simulation Vivado 2017.4

[ Edited ]

Hello Jobin @jobincyriac

 

Thank you very much for sharing your simulation testbench, I have a look on it.

 

1. It seems you are using Native Interface for CSI-2 TX.

2. Please check PG260 Appendix B, Figure B-3 for CSI-2 TX Native interface sample waveform.

3. As stated in PG260, vid_hsync and vid_vsync is High-active signal. Please fix the testbench.

4. When vid_vsync is asserted , MIPI CSI-2 TX will send packet for Frame-Start

5. vid_hsync should keep high, when you are sending your video data.

6. Please set at least 1 period of s_axis_aclk for HBP/HFP. ( we will update PG260 for future release )

7. Data type for RAW8 is 0x2A, you set it as 0x28 ( which mean RAW6) .

 

Please modify your testbench so MIPI CSI-2 TX can send data correctly,

we can discuss the RX part if you have a further problem.

 

Best regards

Leo

CSI2_DATA_TYPE.png
Visitor
Posts: 9
Registered: ‎06-11-2018

Re: MIPI CSI-2 Rx simulation Vivado 2017.4

Thank You @karnanl.

 

With the suggestions you gave, we could able to generate the Rx traffic. Now there are issues with the data integrity, The Rx data does not fully match with the Tx data. 

 

Thank You very much for your support.

 

Regards,

Jobin 

 

 

 

 

Moderator
Posts: 3,756
Registered: ‎11-09-2015

Re: MIPI CSI-2 Rx simulation Vivado 2017.4

HI @jobincyriac,

 

Could you create a new topic for the signal integrity issue? It would be better for other members having the same issues finding an answer.

 

Thanks,

Florent
Product Application Engineer - Xilinx Technical Support EMEA
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