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Visitor nils_optics
Visitor
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Registered: ‎09-25-2018

MIPI CSI-2 TX with external PLL/MMCM clocking

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 I'm attempting to implement Xilinx's MIPI CSI TX module with clocking generated outside the module (options for the module are inside and outside generated clocks)

From the documentation it states that an example design can be generated with MMCM/PLL clocking generated outside the design but the example design is only generated with clocks inside. So I don't have a reference to follow about how to split the clocks between the PLL and MMCM, nor can I see why both of these are required to be used, as I'd prefer to use only one to save power.

I'm using Vivado 2019.1 and the MIPI csi2-tx IP is in a Block Design. 

I tried "Open IP Example Design..."  with both settings:
  "include Shared Logic outside Subsystem"  and
  "include Shared Logic in core"

In both case it creates an example design that hides the clock generation inside the MIPI csi2-tx module.

Is there a way generate the externally generated clocking example or another existing example of external PLL/MMCM used with the MIPI CSI2-TX IP?

-thanks, Nils 

 

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Xilinx Employee
Xilinx Employee
376 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 TX with external PLL/MMCM clocking

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Hello @nils_optics 

As mentioned in the PG, We only recommend Master IP -> Slave IP clock connectivity.

(Unfortunately) If you want modify the clock module for your usecase, you have to do it yourself.
Please generate MIPI D-PHY TX Example Design, try to find mipi_dphy_0_clock_module.v ( or similar filename) which is the clock module contain PLL and MMCM. This is unencrypted RTL, so you can modify this module to fit your own usecase.

CLOCK_MODULE.png

Thanks & regards
Leo

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Xilinx Employee
Xilinx Employee
436 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 TX with external PLL/MMCM clocking

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Hello Nils @nils_optics 

Okay, Perhaps the document is a bit confusing. I agree on that.
The current MIPI CSI-2 TX Example Design only generated MIPI CSI-2 TX with a fixed configuration.


Anyway, the following pictures from PG260 explained how to use IP shared logic.

You need to generate one IP (master IP) with "Include Shared Logic in Core"
and generate the rest of the IP (slave IPs) with "Include Shared Logic in Example Design"
See Figure 3-3 to connect IP clock and reset.

MIPI_TX_Master_Slave.png


Hope this helps. Please let me know if you have a question

Regards
Leo

Visitor nils_optics
Visitor
402 Views
Registered: ‎09-25-2018

Re: MIPI CSI-2 TX with external PLL/MMCM clocking

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I've only got one MIPI port in the design so master/slave chaining them doesn't apply.

I want to locate the PLL/MMCM's outside of the MIPI module so that I can generate 2 addional frequencies used elsewhere in the FPGA.

From looking at the Power Estimate export, I can see that only about 1/2 of each of the PLL and MMCM clock outputs are being utilized by the MIPI module.

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Xilinx Employee
Xilinx Employee
377 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 TX with external PLL/MMCM clocking

Jump to solution

Hello @nils_optics 

As mentioned in the PG, We only recommend Master IP -> Slave IP clock connectivity.

(Unfortunately) If you want modify the clock module for your usecase, you have to do it yourself.
Please generate MIPI D-PHY TX Example Design, try to find mipi_dphy_0_clock_module.v ( or similar filename) which is the clock module contain PLL and MMCM. This is unencrypted RTL, so you can modify this module to fit your own usecase.

CLOCK_MODULE.png

Thanks & regards
Leo

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Visitor nils_optics
Visitor
355 Views
Registered: ‎09-25-2018

Re: MIPI CSI-2 TX with external PLL/MMCM clocking

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This is exactly what I was looking for, thanks!

Xilinx Employee
Xilinx Employee
341 Views
Registered: ‎03-30-2016

Re: MIPI CSI-2 TX with external PLL/MMCM clocking

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Hello @nils_optics 

I forgot one thing.
MIPI clock module has different configuration depends on the line-rate.
So, please ensure you generate MIPI D-PHY TX example design with exactly the same line-rate that you used for your CSI-2 IP.

Regards
Leo

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