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Observer jhallen
Registered: ‎03-23-2017

MIPI DSI Tx subsystem startup


I'm trying to implement a reduced latency video pipeline, so I want the sycnronize the video source with the destination to keep buffering to a minimum.  The MIPI DSI Tx subsystem has its own video timing generator within it, so I need to be careful how I synchronize with it.  There is a core enable bit.  Can anyone tell me if the video timing generator in the DSI Tx is free running, or does it start when the core enable bit is asserted?  If it's free running, then there can be a one frame delay between core enable, and video starts going.  If the timing generator starts when core enable is asserted, then there is a few lines delay only.

Some related questions: Is there any easier way to start the DSI Tx from FPGA logic other than generating AXI transactions?  I was hoping for a control line...

Is there any way to access the vsync and hsync generated by the DSI Tx core?




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Xilinx Employee
Xilinx Employee
Registered: ‎03-30-2016

Re: MIPI DSI Tx subsystem startup

Hello Joe @jhallen 

1. The timing generator inside MIPI DSI controller will start when the core enable bit is asserted.

2. Unfortunately, user cannot access vsync/hsync directly.
As mentioned in the PG238 that The controller must be programmed with required timing values for video data transfer. Please refer Example Timing Register Calculations in PG238 Chapter3.