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2,829 Views
Registered: ‎02-06-2018

MIPI clock lane requirements for MIPI Rx IP

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In our design we use Omnivision 13850 sensor connected to Artix 7 using resistor bridge method (as per XAPP894)

The issue is that the if the sensor is configured for continuous clock, the INIT_DONE bits on CL_STATUS and DL_STATUS are always zero. If I change the clock to gated, so that during LP interval the clock is at zero, i get INIT_DONE bits but the CL_STATUS shows state as 2b'00. Is there a requirement for the clock to include LP transitions? I don't think this sensor support that

 

State of STATUS registers:

CL_STATUS: 0x00000018

DL_STATUS: 0x00000009

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2,717 Views
Registered: ‎02-06-2018

Re: MIPI clock lane requirements for MIPI Rx IP

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After some experiments and based on some of the information in this thread I came up with the following procedure to ensure successful MIPI CSI receiver initialization:

1. Configure the camera but do not start streaming. For Omnivision cameras at least this results in clock and data lanes staying in LP-11  state (1.2V)

2. Initialize and start CSISS IP

3. Start camera streaming (usually a single register write).

 

This is contrary to the typical practices recommended by some other MIPI IP implementations (e.g. Nvidia Tegra SOC) where you need to ensure streaming is active before activating receiver. Nevertheless it seems to work fine and does not require gated clock.

11 Replies
Scholar austin
Scholar
2,789 Views
Registered: ‎02-27-2008

Re: MIPI clock lane requirements for MIPI Rx IP

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Did you check your clock waveform to see it complies?

 

Did you verify your signal integrity of the design?

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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2,778 Views
Registered: ‎02-06-2018

Re: MIPI clock lane requirements for MIPI Rx IP

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Yes and yes, however this is irrelevant.

We managed to "fix" the problem by physically bridging clk_lp +/- to d0_lp +/-. Once this has been done, the receiver started to work without errors.

Which essentially confirms my theory that Xilinx D-Phy implementation as configured by CSI RX requires to see LP transitions on the clock line - which in my opinion is a spec violation

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Scholar austin
Scholar
2,775 Views
Registered: ‎02-27-2008

Re: MIPI clock lane requirements for MIPI Rx IP

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Probably true,


This was an ancient document, no longer being referenced or used.  It was designed to allow something to work when we clearly had nothing.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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2,764 Views
Registered: ‎02-06-2018

Re: MIPI clock lane requirements for MIPI Rx IP

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Apologies, but I don't see how this document being out of date changes anything. The only reason I referred to it was because it had a description of the resistor bridge - which is a perfectly valid solution from EE standpoint (and has been tested and simulated). The issue here is the behavior of th D-Phy receiver, that appears to expect LP transitions on the clock lane in order to function. 

 

Either I've deduced the D-Phy IP behavior correctly (black box, you know) in which case this a a MIPI spec violation, or I am seeing a side effect of something else, and consequently it would be nice to hear what else could it be

 

The Meticom switches used in ZCU102 kit cannot pull LP transitions out of thin air, so if that kit works, it means one of the following:

a) The sensor used there can do LP transitions on the clock lane

b) The version of D-Phy IP in Zync library behaves differently

c) I have some other undiagnosed issue and need help with that

 

I would really appreciate a further comment on this

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Xilinx Employee
Xilinx Employee
2,756 Views
Registered: ‎03-30-2016

Re: MIPI clock lane requirements for MIPI Rx IP

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Hello @alexfeinman_daqri

Do you mean that your sensor clock lane is toggling from the start ( even before you start initializing MIPI CSI-2 RX IP) ?
If so, then I believe your sensor does not follow the MIPI spec correctly.

 

Xilinx MIPI IP cannot do calibration properly without LP-11 on MIPI input pin.
D-PHY spec (section 6.11) stated this requirement clearly. Please keep D-PHY clock/data lane at LP-11 before you start the initialization process.


Also ensure that :
    1. All MIPI IP clocks are stable
    2. Minimum of 40 core_clk cycles of reset period ( as suggested by PG202)

INIT_DONE should be asserted if you follow above guidance.


Thanks & regards

Leo

MIPI_SPEC.png
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Visitor igor.komir
Visitor
2,744 Views
Registered: ‎08-23-2017

Re: MIPI clock lane requirements for MIPI Rx IP

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Hello, Leo -

We are discussing the behavior of CSI-2 RX controller, not pure D-PHY.

Section 7.1 (D-PHY Physical Layer Option) of MIPI CSI-2 spec states, that continuous clock (always remaining in HS) not only allowed but is mandatory:

 

 

An absence of continuous clock support in MIPI CSI-2 Rx Controller IP is a violation of MIPI  CSI-2 spec. 

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Xilinx Employee
Xilinx Employee
2,730 Views
Registered: ‎03-30-2016

Re: MIPI clock lane requirements for MIPI Rx IP

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Hello @igor.komir, @alexfeinman_daqri
Thanks for responding,  Yes I am aware that all CSI-2 transmitters and receivers shall support continuous clock mode.

PG232 did not mention that CSI-2 RX IP does not support cont-clock mode.

 

What I want to confirm is, when you started to initialize MIPI CSI-2 RX IP

1. Is your MIPI IP input clock at stable condition ? 

2. Is the sensor already transmitting LP-11 ?    

3. Does your sensor keep the clock lane in LP-11 for more than T-INIT period ?

RX will not be able to finished the initialization sequence without observing LP-11 on its input for more than T-INIT(SLAVE) period.

Best regards

Leo

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Visitor igor.komir
Visitor
2,716 Views
Registered: ‎08-23-2017

Re: MIPI clock lane requirements for MIPI Rx IP

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Hello, Leo - 

Answering your questions:

1. Yes, MIPI IP clock in stable condition.

2. As FPGA initializes longer than the sensor, we have to hold the sensor in reset/power-down mode to prevent it from HS clock transmission during MIPI CSI-2 Rx initialization. There is no guarantee that clock is in LP-11 during reset.

3. Releasing the sensor out of reset results STOP condition on clock lanes followed by the transition to HS clock. However, reliable synchronization between sensor out-of-reset transition and CSI-2 RX IP init is hard to get, as both processes are microcode/FW driven.  

4. Changing sensor's setting to generate HS -> LP -> HS transition every video frame allowed it work reliably with Xilinx CSI-2 Rx IP.

 

Thank you for your help.

- Igor.

 

 

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Moderator
Moderator
2,406 Views
Registered: ‎11-09-2015

Re: MIPI clock lane requirements for MIPI Rx IP

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Hi @igor.komir and @alexfeinman_daqri,

 

Is everything clear for you? If yes could you kinldly close the topic by marking the best reply as accepted solution.

 

Else please reply with your current status.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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2,718 Views
Registered: ‎02-06-2018

Re: MIPI clock lane requirements for MIPI Rx IP

Jump to solution

After some experiments and based on some of the information in this thread I came up with the following procedure to ensure successful MIPI CSI receiver initialization:

1. Configure the camera but do not start streaming. For Omnivision cameras at least this results in clock and data lanes staying in LP-11  state (1.2V)

2. Initialize and start CSISS IP

3. Start camera streaming (usually a single register write).

 

This is contrary to the typical practices recommended by some other MIPI IP implementations (e.g. Nvidia Tegra SOC) where you need to ensure streaming is active before activating receiver. Nevertheless it seems to work fine and does not require gated clock.

Moderator
Moderator
1,553 Views
Registered: ‎11-09-2015

Re: MIPI clock lane requirements for MIPI Rx IP

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Hi @alexfeinman_daqri,

 

Thank you for sharing. As it is working for you, could you kindly close the topic by marking your last reply as accepted solution?

 

Thanks


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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