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Adventurer
Adventurer
846 Views
Registered: ‎05-28-2018

Minimum number of API calls to get a VPSS Deinterlacer-Only IP block running

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So, we have a dual Video pipline working well in progressive mode with all necessary resolutions and frame-rates. We've been working to including interlaced video support. We have 64K Local Memory built for the Microblaze susbsystem for controlling VDMAs, RTL blocks, and VTCs.

As a 2nd strategy, we decided to add deinterlacers just before the VDMA blocks. The VPSS was instantiated and configured for Deinterlace Only, no Adaptive Motion Filtering at first. Our defult microblaze "starter" code, which warms up the HW, which programs the VDMAs and VTCs and starts the piplines, takes 18K. I started adding the declarations and routines for starting the VPSS, and this small block of code JUMPED to 131K making it necessary to allocate 256K for the Microblaze, which is NOT ideal. All of our DRAM is going to be used for Video Frame Buffers, so is off-limits to the Microblaze.

Here's how I'm initializing the system. Please tell me that I've done too much. That call to XVprocSs_LookupConfig pulls in lib support and takes up almost 124K of code memory!!  Wow!

#include <stdio.h>
#include "xparameters.h"
#include "xil_types.h"
#include "xstatus.h"
#include "xil_testmem.h"
#include "vdma.h"
#include "vdma_api.h"
#include "platform.h"
#include "memory_config.h"
#include "xil_printf.h"
#include "xil_io.h"

/*** Global Variables ***/
unsigned int srcBuffer = (XPAR_MIG7SERIES_0_BASEADDR  + 0x1000000);

static XVprocSs VprocInst_0;
static XVprocSs VprocInst_1;

...

int main()
{
int i;

// initalize all v_proc_ss (v_deinterlacer) data structures and variables
XVprocSs_Config *VprocSsConfigPtr_0;
XVprocSs_Config *VprocSsConfigPtr_1;

XVprocSs *pVprocss_0;
XVprocSs *pVprocss_1;

    pVprocss_0 = VprocInst_0;                              // are these pointers getting set up correctly?
    pVprocss_1 = VprocInst_1;
    memset(pVprocss_0, 0, sizeof(XVprocSs));

    memset(pVprocss_1, 0, sizeof(XVprocSs));      

    init_platform();

...

    xil_printf("Initialize Video Processing Subsystem...\r\n");

    VprocSsConfigPtr_0 = XVprocSs_LookupConfig(XPAR_V_DEINTERLACER_0_DEVICE_ID);

    if (VprocSsConfigPtr_0 == NULL) {
       xil_printf("ERR:: VprocSs device not found\r\n");
    }

    XVprocSs_CfgInitialize(pVprocss_0,
                                 VprocSsConfigPtr_0,
                                 VprocSsConfigPtr_0->BaseAddress);   

    XVprocSs_Start(pVprocss_0);

  

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Moderator
Moderator
741 Views
Registered: ‎11-09-2015

Re: Minimum number of API calls to get a VPSS Deinterlacer-Only IP block running

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HI @gcsimmonsjr ,

Is it for an interlaced input (as you are not using 2018.3)?

I you check the example application, you can see how to enable the journal log. This might give you some details.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
14 Replies
Adventurer
Adventurer
814 Views
Registered: ‎05-28-2018

Re: Minimum number of API calls to get a VPSS Deinterlacer-Only IP block running

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I think I found one thing. We need to call XVProcSs_SetSubsystemConfig. However, if you call that, and leave the Vivado / System defaults in place, this routine errors out at ValidateDeintOnlyConfig, because the system default is Input Stream 1080P@60/RGB+Output Stream 1080P@60/RGB, and this will cause the very first validation step in this routine to fail:

      if ((pStrmIn->IsInterlaced != TRUE) || (pStrmOut->IsInterlaced != FALSE)) {
        XVprocSs_LogWrite
(XVprocSsPtr, XVPROCSS_EVT_CFG_DEINT, XVPROCSS_EDAT_INTPRG);
        return
(XST_FAILURE);
    }

So ... of course, we can set the Input stream to 1080i and it will pass this check, but what if I DO have a 1080p@60/RBG stream coming in????

PG231-v-proc-ss.pdf says that you can set the Deinterlacer Bypass Mode by setting register 0x38 to 6. However, there are TWO problems with this:

1) First, there should be an API cal lto do this, right??

2) This WILL NOT resolve the issue of the ValidateDeintOnlyConfig routine getting called and failing when receiving a 1080P signal.

So, I must be missing a few things here. Where's the API call to set the Deinterlacer Bypass Mode, and what mechanism is in place in all of layers of XVProcSS_SetSubsystemConfig to avoid trying to ValidateDeintOnlyConfig when it's bypassed???

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Adventurer
Adventurer
791 Views
Registered: ‎05-28-2018

Re: Minimum number of API calls to get a VPSS Deinterlacer-Only IP block running

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Addtional:   I found this forum article which addresses the Deinterlacer algorithm selection via the APIs.

https://forums.xilinx.com/t5/Video/Deinterlacer-Algorithm-Selection/m-p/872954?collapse_discussion=true

This article describes setting the Algo mode before start_system() API, which I assume is XVprocSs_Start(). This gives us a mechanism to turn the Bypass Mode on (which PG231 describes as "... pass[ing] the input of the IP to the output without any change in the data and enable the IP to the function in bypass mode.")  I'm making the general assumption that this is valid for Progressive Mode video like 1080p.

However, the problem we're having is that if you have the Stream Input configured to 1080p, as in the system default, the ValidateDeintOnlyConfig() API will fail.

Suggestions on how to overcome this?


The other thing I'm still puzzled about, is how Deinterlacer Algo Mode 0x06 could meet the bypass description in PG231 "without any change in the data," when in the API description and those by the Xilinx AEs call it "bilineal" mode, which implies a data transformation.

Clarification??

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Moderator
Moderator
778 Views
Registered: ‎11-09-2015

Re: Minimum number of API calls to get a VPSS Deinterlacer-Only IP block running

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Hi @gcsimmonsjr ,

Please start by letting me know which vivado you are using?

The bypass option for the deinterlacer was introduced in 2018.3, at least in the documentation. I agree this is not clear because it is never clearly stated anywhere.

However, it seems that the code is still present in 2018.3 while the bypass mode exists. I will report this to development and let you know.

You might want to modify the driver to remove this check in the meantime.

Regards,

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
766 Views
Registered: ‎05-28-2018

Re: Minimum number of API calls to get a VPSS Deinterlacer-Only IP block running

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OK. All of our designs were started in 2017.1 and are all up to 2017.4.

We're pretty much doing what's been outlined in the documentation and what I've described above in the code. I've got System ILAs on the AXIS input side of the Deinterlacer and on the AXIS output side of the Deinterlacer.

The m_axis_tready signal is a '1', but the s_axis_tready signal from the Deinterlacer core is '0' and we can't seem to get it to change.

Suggestions?

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Moderator
Moderator
742 Views
Registered: ‎11-09-2015

Re: Minimum number of API calls to get a VPSS Deinterlacer-Only IP block running

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HI @gcsimmonsjr ,

Is it for an interlaced input (as you are not using 2018.3)?

I you check the example application, you can see how to enable the journal log. This might give you some details.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Adventurer
Adventurer
730 Views
Registered: ‎05-28-2018

Re: Minimum number of API calls to get a VPSS Deinterlacer-Only IP block running

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Yes, we're trying to support both interlaced and progressive video inputs - in 2017.4.

Are you talking about XAPP1291?   The example application for the Video Processing Subsystem is broken and won't build. There have been several forum posts about this. Maybe it's fixed for 2018.3. I'll look and maybe I can figure out the journal log.

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Minimum number of API calls to get a VPSS Deinterlacer-Only IP block running

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Hi @gcsimmonsjr ,

No I am talking about the example design mentionned in the PG. You need to make sure the HDF is coming from the example design


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
693 Views
Registered: ‎05-28-2018

Re: Minimum number of API calls to get a VPSS Deinterlacer-Only IP block running

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The Journal Log was an excellent suggestion. It has allowed us to go through our initialization procedures, and then dump the Journal Log and see that things were indeed working.

We have the ability to stop the streaming video from the source, via an RTL module, and when we initialized everything, and left the stream off, we could see that the s_axis_tready signal was indeed high as we would have expected.

We then armed the ILAs in the FPGA and opened up the pipe. We could see evidence of the video data moving through the Deinterlacer as it should, but issues downstream with the VDMA caused the deinterlacer to de-assert s_axis_tready. Perhaps an overflow situation.

We are investigating that now.   Thank you for your help!!!   

Adventurer
Adventurer
680 Views
Registered: ‎05-28-2018

Re: Minimum number of API calls to get a VPSS Deinterlacer-Only IP block running

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Can we solicit your help again?

We're kind of stumped. We are seeing all success when configuring th Deinterlacer_Only function of the VPSS, and with no Video Data flowing, s_axis_tready is high. The Deinterlacer is connected directly to a VDMA S2MM interface. When we start moving video data, it appears we get one frame in or a partial frame, and then s_axis_tready goes low. We can't figure out why.

Also, if we configure the input stream and output stream to 1080 progressive video, are the Deinterlacer_Only API routines smart enough to let that video pass without any intervention on our part?  Effectively that bypass mode?  We can't seem to pass even progressive video through the deinterlacer block.

If we bypass the v_procss Deinterlacer Only in Vivato (effectively deleting them,) the whole video path works perfectly with progressive video.

Please help!

Are there any other examples of using the Deinterlacer Only IP that we could look at?

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Moderator
Moderator
647 Views
Registered: ‎11-09-2015

Re: Minimum number of API calls to get a VPSS Deinterlacer-Only IP block running

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Hi @gcsimmonsjr ,

As mentionned previously, I am not sure if the bypass was correctly implemented in the driver in 2018.3. So you might need to implement it by yourself.

Another solution would be to use the VPSS as full fledge because it has the ability to by-bass any subelements. Using the example design as reference should work for a full by-pass (input = output)

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
605 Views
Registered: ‎05-28-2018

Re: Minimum number of API calls to get a VPSS Deinterlacer-Only IP block running

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We implemented the FullVPSS, and this works as expected!  So, what can we conclude from this?

"Individual instances" don't work in 17.4?

BTW, it's clear from studying the BSP for the VPSS that normal blocks like the VDMA are used in this subsystem. It would be VERY helpful if we could see the block diagram for the whole VPSS and how individual blocks are connected in this subsystem - like clicking the "+" sign on an user-built subsystem.

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Minimum number of API calls to get a VPSS Deinterlacer-Only IP block running

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Hi @gcsimmonsjr ,

In the full fledge mode, you can bypass any sub-cores. But this is not the same bypassing. All the subcores are connected using interconnects. Thus, when you are bypassing a sub-cores, the data just does not go to this core.

I have previously asked to have a screenshot of the inside of the VPSS in the documentation but I am not sure it will be in the next version.

The goal is to show the IP as a single core because to simplify everything.

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Adventurer
Adventurer
574 Views
Registered: ‎05-28-2018

Re: Minimum number of API calls to get a VPSS Deinterlacer-Only IP block running

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I understand that they want the core to be seen as a single core, however, that's REALLY in H/W only.

Sometimes, we focus way too much on the H/W and forget the bigger picture, which is the S/W. If you look at how the BSP is put together, with individual device drivers, one can see that this system is put together using separate Xilinx IPs. Any S/W or F/W engineer, worth their salt, can see this after digging in.

For their sake, and ours (2 F/W engineers,) a picture or block diagram of all the components and how they are connected would be very useful.  

Adventurer
Adventurer
527 Views
Registered: ‎05-28-2018

Re: Minimum number of API calls to get a VPSS Deinterlacer-Only IP block running

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BTW, I downloaded Vivado 18.3 Webpack and NONE of the IP was upgraded except for the Microblaze, the Clock Wizard, and the AXIS Data FIFO.  VPSS wasn't touched from 17.4, neither, from what we can tell, was ANY of the API code. 

You mention being able to bypass any sub-core. Is this done using the Video Router API?

Are these APIs called automatically when you configure an input and output streams?  Or, do you have to call these?

This Video Processing Subsystem is EXTREMELY complex, and the API documentation is terse at best. Florentw, we could REALLY use a VERY good Tutorial on this subject: 1) how to set it up with the API's properly, 2) bypassing different sub-cores (automatic? or no?  3) getting standalone cores to work, like the Deinterlacer Only core, 4) expected memory foot-print to allow Full-Fledged VPSS to operate to it's potential (we're at 512K of local memory for Microblaze, and that's disappearing FAST!), 5) what could cause the VPSS to hang/crash, etc.

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