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Explorer
Explorer
1,917 Views
Registered: ‎07-10-2008

Please help with HDMI2.0 error

When we synthesize HDMI2.0 IP, the following error was shown as in attached image.

 

We are using .XC7Z035-2FFG900.

 

Please give us any suggestions about how to fix this error, it is so frustrated.

 

Yours sincerely.

 

David.无标题.png

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6 Replies
Explorer
Explorer
1,840 Views
Registered: ‎07-10-2008

Re: Please help with HDMI2.0 error

If it is possible please shot me any suggestions.

 

Any helps are appreciated

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Xilinx Employee
Xilinx Employee
1,828 Views
Registered: ‎08-02-2007

Re: Please help with HDMI2.0 error

From the screenshot, it looks like rx_tmds_clk isn't properly constrained in IPI. Can you provide following information, please?

1. Open synthesized design, and then type "report_clocks" in tcl console, and then attach the generated clock report.

2. Take a screenshot for your design, showing the clock structure of your design, especially how you drive rx_tmds_clk.

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Explorer
Explorer
1,801 Views
Registered: ‎07-10-2008

Re: Please help with HDMI2.0 error

Please check the attached files including schematic and FPGA report, etc.

 

By the way, we are using the evaluation license, dose this matters?

 

Any helps are appreciated.

1.png

1.png

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Explorer
Explorer
1,799 Views
Registered: ‎07-10-2008

Re: Please help with HDMI2.0 error

One file forgotten attaching is as below.

 

vid_phy_error.PNG
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Explorer
Explorer
1,655 Views
Registered: ‎07-10-2008

Re: Please help with HDMI2.0 error

Please let us know if there are any updates for this HDMI2.0 error?

 

Many thanks,

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Xilinx Employee
Xilinx Employee
1,645 Views
Registered: ‎08-02-2007

Re: Please help with HDMI2.0 error

The report you attached isn't associated to the design which has original error : 

1. In the error message, the MMCM is called hdmi_4/inst/RXPLL_INST, I guess the design name is called hdmi_4. While in the report, it's called 

hdmi_phy_1/inst/RXPLL_INST/

 2. In the error message, the period for hdmi_4/inst/RXPLL_INST/CLKIN is 1.667. While the period for hdmi_phy_1/inst/RXPLL_INST/CLKIN1 is 8 ns

 

 So I doubt whether you are debugging the same design.

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