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Participant futureishere
Participant
748 Views
Registered: ‎12-04-2014

Problem activating all four lanes dynamically for MIPI CSI-2 Tx Subsystem IP

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I have configured the mipi csi-2 tx subsystem IP to use four lanes, and activate all four lanes by writing to the configuration register. But, as per d-phy dl_status register, the IP only sends data on first two lanes. I have verified that the configuration register is set correctly. I tested with both dual and quad pixel per beat modes, but the result is the same. Then I disabled the active lanes option in MIPI IP so that all four lanes are active by default. This did the trick and now data is being sent on all four lanes as expected. Is it a known bug in the IP (I am using the version included in Vivado 2017.4) or am I missing something?

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Moderator
Moderator
615 Views
Registered: ‎10-04-2017

Re: Problem activating all four lanes dynamically for MIPI CSI-2 Tx Subsystem IP

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@futureishere,

 

If you are not able to switch lanes at all, this tells me that the core does not see that the lanes are in "Stop State".

"All the interrupts are masked" - can you unmask the interrupts to get more status from the core?

2018-12-07 12_04_10-Xilinx Documentation Navigator 2017.2 -  http___www.xilinx.com_support_documenta.png2018-12-07 12_05_38-Xilinx Documentation Navigator 2017.2 -  http___www.xilinx.com_support_documenta.png

Regards,

Sam

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
5 Replies
Moderator
Moderator
702 Views
Registered: ‎10-04-2017

Re: Problem activating all four lanes dynamically for MIPI CSI-2 Tx Subsystem IP

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Hi @futureishere,

To summarize:

  1.  you have a MIPI CSI-2 TX SubSystem connected to hardware that is capable of 4-lane a configuration.
  2. When you do not select active lanes, the system works with 4 lanes as reported by the d_phy
  3. When you do select active lanes, the system only sends on 2 of the 4 lanes.

This is not a known issue in the IP as far as I know.

 

Questions:

  1. When is the protocol configuration registers bits 1:0 set to 0x3? (what stage in initialization, time 0 or later) 
  2. What is the value of the protocol configuration register?
  3. Do you have the interrupt for Incorrect lane configuration unmasked? Is this interrupt going high?
  4. Are you able to switch from 2 lanes to 1 lane in the case where the 4-lane configuration does not work?

For reference, I am pasting the active lane configuration requirements from PG260

2018-12-02 08_11_42-Xilinx Documentation Navigator 2017.2 -  http___www.xilinx.com_support_documenta.png

-Sam

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
Participant futureishere
Participant
648 Views
Registered: ‎12-04-2014

Re: Problem activating all four lanes dynamically for MIPI CSI-2 Tx Subsystem IP

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  1. When is the protocol configuration registers bits 1:0 set to 0x3? (what stage in initialization, time 0 or later) 
  2. What is the value of the protocol configuration register?
  3. Do you have the interrupt for Incorrect lane configuration unmasked? Is this interrupt going high?
  4. Are you able to switch from 2 lanes to 1 lane in the case where the 4-lane configuration does not work? 

Hi Sam,

 

Thanks for your reply. To answer your questions:

  1. The software does a soft reset to the core by writing to 0x2 to the core config register and waits for the controller ready bit to go high before writing to protocol config register to activate the lanes.
  2. The protocol config register value is 0x0000201B (for dual pixel mode, max 4 lanes, active 4 lanes).
  3. All the interrupts are masked, the incorrect lane config interrupt doesn't go high.
  4. I am not able to switch from 2 lanes to 1 lane either!
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Moderator
Moderator
616 Views
Registered: ‎10-04-2017

Re: Problem activating all four lanes dynamically for MIPI CSI-2 Tx Subsystem IP

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@futureishere,

 

If you are not able to switch lanes at all, this tells me that the core does not see that the lanes are in "Stop State".

"All the interrupts are masked" - can you unmask the interrupts to get more status from the core?

2018-12-07 12_04_10-Xilinx Documentation Navigator 2017.2 -  http___www.xilinx.com_support_documenta.png2018-12-07 12_05_38-Xilinx Documentation Navigator 2017.2 -  http___www.xilinx.com_support_documenta.png

Regards,

Sam

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
Participant futureishere
Participant
573 Views
Registered: ‎12-04-2014

Re: Problem activating all four lanes dynamically for MIPI CSI-2 Tx Subsystem IP

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Hi,

 

As it turns out, there was a bug in our software code as a result of which, we were not writing to the protocol config register properly. After fixing that bug, we are able to change the number of lanes dynamically. Sorry about that.

Moderator
Moderator
561 Views
Registered: ‎10-04-2017

Re: Problem activating all four lanes dynamically for MIPI CSI-2 Tx Subsystem IP

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No problem and thank you for confirming! I am glad you were able to get to a solution.

 

-Sam

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