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Newbie tejna
Registered: ‎01-08-2019

Problem after creating IP for a previously successful design


I am fairly new to developing projects using FPGAs especially using Vivado tools. I am working on developing a graphics application on Arty S7 development board which has the Spartan7 FPGA. When I create the project just using VHDL, I am able to see the graphics output on screen. But when I create an IP core for the project and add Microblaze to it using IP Integrator, and export the hardware to SDK to program it, I am not able to see the right output on screen. I can just see a black screen, so not sure where I am going wrong. I was wondering if it has anything to do with clocking or timing. Again I am really sorry if the question seems basic, but do we have to add separate timing constraints file for the project? Because when I did the same project using Xilinx ISE, there was no need for manual timing constraints.

Thank you so much in advance for your time and help.


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Registered: ‎11-09-2015

Re: Problem after creating IP for a previously successful design

HI @tejna,

There are multiple possible root cause to your issue. This is nearly impossible to say without debugging.

You might want to run simulations or add an ILA to check what is going on.

Product Application Engineer - Xilinx Technical Support EMEA
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