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Visitor chenhai
Registered: ‎02-14-2008

Question about FIR compilers in Hardware co-simulation.

Hello all,
I am now trying to filter an image with the hardware co-simulation by p2p ethernet.
The FIR filter compilers(1.0-3.1) with 41 coefficients work correctly at the software simulation stage.
However, it do nothing after generating the LIB with system generator and downloading into the FPGA.
Is that any parameter uncorrect? Or is the coefficient  too many?
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1 Reply
Xilinx Employee
Xilinx Employee
Registered: ‎08-07-2007

Re: Question about FIR compilers in Hardware co-simulation.

You should use the latest version of the FIR Compiler available in System Generator which is v3.1.  The number of coefficients you've chosen is perfectly valid. 

I suspect the problem may be with your hardware co-simulation setup.  You may want to try a basic "pass through" design with a couple registers only to confirm that your hardware co-simaultion is set up properly before moving on to a more complex design.
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