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Adventurer
Adventurer
1,233 Views
Registered: ‎08-26-2017

Scalar (VPSS) with HDMI In Out Pipeline

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Hi,

 

For one of our applications we need to scale an input video to 4K@60FPS. The video input and output is through HDMI Interface.

 

Therefore, we have generated a HDMI pass through example design targeting ZCU102 board and added VPSS in scalar only mode to the video pipeline. 

 

Example Design Base Pipeline

HDMI RX -> TPG -> HDMI TX

 

Modified Design Pipeline

HDMI RX -> TPG -> VPSS(Scalar Only) -> HDMI TX.

 

As per the example design Video Clock is 300MHz.We have used the same for VPSS as well.

 

The block design's PDF is attached for reference.

 

We did the necessary, software modifications with respect to VPSS initialisation and configuration. Our intention is to scale the video input through HDMI to UHD@60FPS or FHD@60FPS.

 

We are facing two problems when we are trying to fix the output resolution different than that of input resolution. We do not see HDMI TX getting locked to input stream. 

 

Trial 1:

VPSS is configured in RX stream up call back function

Case 1 -> VPSS input and output stream parameters are same as that of HDMI RX stream parameters

Result -> We could see the input video on the output display. The changes in input are reflected in output. We could see HDMI TX Lock status LED ON.

Case 2 -> VPSS input configured with HDMI RX stream parameters. VPSS output and HDMI TX are configured with user entry parameters(either run time using UART terminal or hardcoded in code)

Result -> We could not see any display in the output. We could see the HDMI TX Lock status LED OFF, indicating that HDMI TX is not locked.

 

Case 3 -> Same as Case 1, but OutFreq parameter in I2CClock function(HDMI TX Ref **bleep** Source Si5324 Program function) set to calculated(based on VmID) frequency instead of RX TMDS clock frequency.

Result -> No display in the output. HDMI TX Lock Status LED OFF.

 

Case 4 -> Same as Case 2, but OutFreq parameter in I2CClock function(HDMI TX Ref **bleep** Source Si5324 Program function) set to calculated(based on VmID) frequency instead of RX TMDS clock frequency.

Result -> No display in the output. HDMI TX Lock Status LED OFF.

 

Trial 2: 

VPSS is configured in Enable colorbar function.

Case 1 -> VPSS input and output stream parameters are same as that of TPG output

Result -> We could not see the display at powerup, however when we changed the TPG resolution through UART we could see the display in the output and also HDMI TX Lock Status LED as ON.

 

Case 2 -> VPSS input parameters are same as that of TPG output. VPSS output stream and HDMI TX stream parameters set to UHD@60FPS

Result -> No display in the output. HDMI TX Lock Status LED OFF.Tried with multiple TPG resolutions.

 

Case 3 -> VPSS input parameters are same as that of TPG output. VPSS output stream and HDMI TX stream parameters set to FHD@60FPS

Result -> No display in the output. HDMI TX Lock Status LED OFF. Tried with multiple TPG resolutions.

 

Case 4 -> VPSS input parameters are same as that of TPG output. VPSS output stream and HDMI TX stream parameters set to HD@60FPS

Result -> We could see the display in the output for all resolutions less than or equal to HD. HDMI TX Lock Status LED was ON. For resolutions greater than HD, there was no display in the output. 

 

We could not understand why this is happening. Any suggestion in this regards would be of great help.

 

I have attached the main c file for reference(xhdmi_example.c) 

 

Thanks and Regards,

Ajay Kumar G

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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Adventurer
Adventurer
1,598 Views
Registered: ‎08-26-2017

Re: Scalar (VPSS) with HDMI In Out Pipeline

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Hi Florent,

We were logging the VPSS info after configuring the VPSS using Report function. It shows the input and output config details as expected. We have also logged the calculated TMDS clock for the given output config which also shows the expected values.

We tried adding the VPSS - HDMI TX - VPHY data pipeleine to ILA but therewas a DRC violation on the SI_5324_LOL_In pin with respect to in buffer. The same was resolved when debug is cleared from the same. We have not yet retried that.

I will post the results on ILA and VDMA soon.

Thanks and Regards,
Ajay Kumar
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3 Replies
Moderator
Moderator
1,181 Views
Registered: ‎11-09-2015

Re: Scalar (VPSS) with HDMI In Out Pipeline

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Hi @ajaykumargurrala,

 

You might want to output some logs from the VPSS to see if everything is fine.

 

You can also add an ILA at the output of the VPSS to see if you have data coming out.

 

It might be that the VPSS does not have enough time to generate the video data. You might want to add a VDMA after the VPSS.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Tags (3)
0 Kudos
Adventurer
Adventurer
1,599 Views
Registered: ‎08-26-2017

Re: Scalar (VPSS) with HDMI In Out Pipeline

Jump to solution
Hi Florent,

We were logging the VPSS info after configuring the VPSS using Report function. It shows the input and output config details as expected. We have also logged the calculated TMDS clock for the given output config which also shows the expected values.

We tried adding the VPSS - HDMI TX - VPHY data pipeleine to ILA but therewas a DRC violation on the SI_5324_LOL_In pin with respect to in buffer. The same was resolved when debug is cleared from the same. We have not yet retried that.

I will post the results on ILA and VDMA soon.

Thanks and Regards,
Ajay Kumar
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Moderator
Moderator
1,110 Views
Registered: ‎11-09-2015

Re: Scalar (VPSS) with HDMI In Out Pipeline

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Hi @ajaykumargurrala,

 

Do you have any updates on this.

 

If it is solved, please kindly post your finding to help others and mark your reply as accepted solution.

 

Thanks,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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