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Newbie adouraghy
Newbie
5,822 Views
Registered: ‎11-07-2007

System Generator 8.1i --- Period of the Constraint??

Anyone,
My SysGen model passes the timing analysis (No negative skew and the highest logic level is 19). TRACE reports 0 timing errors.
However, when trying to generate a bitstream it will fail at the very end.
Searching the details I find the following error:
 
WARNING:Timing:3232 - Timing Constraint
   "TS_RCH_RXCLK = PERIOD TIMEGRP "RCH_RXCLK" 2 ns HIGH 50%;"
    fails the minimum period check for clock U_top/u_custom_logic/u_sysgen/u_rch_rx_data_l/rxclk_sig because the period
   constraint value (2000 ps) is less than the minimum internal period limit of 4000 ps.   Please increase the period of
   the constraint to remove this timing failure.
 
Followed by:
 
Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.
 
------------------------------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of
                                            |            |            | Levels | Slack      |errors  
------------------------------------------------------------------------------------------------------
* TS_U_top_adac_dcm_clk_sig = PERIOD TIMEGR | 10.000ns   | 10.634ns   | 10     | -0.634ns   | 13     
  P "U_top_adac_dcm_clk_sig"         TS_ACQ |            |            |        |            |        
  UISITION_CLK HIGH 50%                     |            |            |        |            |        
------------------------------------------------------------------------------------------------------
 
It seems this is the only constraint holding up my design, but I have no idea how to solve it. If the solution is related to increasing the period of the constraint... how do I do that in SysGen?
Any help would be extremely appreciated. Thanks.
 
-Ali
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1 Reply
Explorer
Explorer
5,802 Views
Registered: ‎08-14-2007

Re: System Generator 8.1i --- Period of the Constraint??

You can change the period constraint by changing the value of FPGA clock period (Double click System Generator icon in Simulink model, you'll see it). The default value is 10 ns. According to the table you pasted, there are 13 timing errors. Please try to increase period constraint.
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