UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor tkuseler
Visitor
2,071 Views
Registered: ‎02-04-2010

System Generator, own: Xilinx JTAG Hardware Co-simulation Block

Dear All!

 

Is it possible to create an own (individual configured) Xilinx JTAG Hardware Co-simulation Block in the System Generator without generating the block inside System Generator?

The idea is, the generate the bit-File outside the System Generator software and use System Generator / MatLab only for generating and analysing data.

 

I saw that it is possible to change the bitstream name in the Co-Sim block but how can I change ports etc.?

A default/empty "JTAG Co-sim" doesn't seem to be exist in the library.

 

Thanks in advance!

 

Torben

0 Kudos