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Participant hariprasadb
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Registered: ‎04-23-2018

Timing parameters for 4K (UHD 3840 x 2160 ) resolution

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Hello,

 

We are targetting 4K (UHD 3840 x 2160 ) resolution on KCU105 platform using Xilinx's UHD SDI IP by making use of Inrevium FMC card. I have refered to XAP1248 to create a platform for Full-HD resolution and it is working fine.

We are upgrading the design to 4K and currently working on SDI output path (SDI TX) by configuring SDI IP into 12G-8DS mode with a test pattern 7.0.

Along with TPG7.0, we need to use Timing controller in Generator Mode. VTC doesn't have inbuilt timing parameters for 4K resolution.

Has anybody came across the timing parameters needs to applied for VTC IP for 3840 X 2160 @60fps ? I have attached the parametres with one set of values, but I am seeing the Vblank and vsync toggling is not proper.

 

With Regards,

Hariprasad

4k.png
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Moderator
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Registered: ‎11-09-2015

Re: Timing parameters for 4K (UHD 3840 x 2160 ) resolution

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HI @hariprasadb,

 

The drivers (when using the AXI4-Lite interface) can be used to program 4K. It will call the drvier video_common_v4_3 (<Xilinx installtion path>\SDK\2018.1\data\embeddedsw\XilinxProcessorIPLib\drivers\video_common_v4_3\).

If you check in the file xvidc_cea861.h, you will have timing configuration for 4K.

 

Hope that helps,

 

Regards,

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Timing parameters for 4K (UHD 3840 x 2160 ) resolution

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HI @hariprasadb,

 

The drivers (when using the AXI4-Lite interface) can be used to program 4K. It will call the drvier video_common_v4_3 (<Xilinx installtion path>\SDK\2018.1\data\embeddedsw\XilinxProcessorIPLib\drivers\video_common_v4_3\).

If you check in the file xvidc_cea861.h, you will have timing configuration for 4K.

 

Hope that helps,

 

Regards,

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Participant hariprasadb
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Registered: ‎04-23-2018

Re: Timing parameters for 4K (UHD 3840 x 2160 ) resolution

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Hello florentw

 

 

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Participant hariprasadb
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Registered: ‎04-23-2018

Re: Timing parameters for 4K (UHD 3840 x 2160 ) resolution

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Hello,

 

Refering to xvidc_timing_table.c, I am updating the VTC. But, looks like these parameters are not exact. 

I have microblaze project, where it is working fine till 1080P . In the same project, I updated the timing parameters for UHD (3840x2160@60Hz).

I am seeing the tready of AXIS to Vid out IP is deasserted after some time. and the userguide says

(https://www.xilinx.com/support/documentation/ip_documentation/v_axi4s_vid_out/v3_0/pg044_v_axis_vid_out.pdf , page 54) it can happen due to internal FIFO almost full status or improper VTC timing. For UHD resolution AXIS clock is 300MHz and Vid_out_clk is 297MHz. There could be no issue with FIFO almost full since, lower resolution (AXIS clock = 300MHz and Vid_out_clk = 148.5MHz) is working fine. Also, I have enabled maximum depth of 8K for "AXI4-Stream to Video Out" IP.

So, I am attaching the main.c file. Can you please check the vtc configuration part and comment on that?

 In between, I am using Vivado 2017.4.

With Regards,

Hariprasad

 

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Moderator
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Registered: ‎11-09-2015

Re: Timing parameters for 4K (UHD 3840 x 2160 ) resolution

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Hi @hariprasadb,

 

You should still check the output overflow and underflow for the AXI4-STREAM to video out.

 

I doubt the parameter are wrong for 4K as it is used successfuly by other IPs as Dp (even if it could but I prefer checking the status o the AXI4S to video out first).


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Participant hariprasadb
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Registered: ‎04-23-2018

Re: Timing parameters for 4K (UHD 3840 x 2160 ) resolution

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Hi Florent,

 

Thanks for your quick reply.

Yes, I have triggered for Overflow and underflow status independently. But, none are asserting. 

 

With Regards,

Hariprasad

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Participant hariprasadb
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Registered: ‎04-23-2018

Re: Timing parameters for 4K (UHD 3840 x 2160 ) resolution

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Hi,

 

I debugged further and noticed that when I configure VTG (Timing Generator) for 2160P resolution, vtg_hblank is not toggling, but vtg_vblank toggles but not as expected. But, in the same project, If I input 1080P or 720P resolution, vtg behaviour is proper and output video is good.

Is it possible to comment on the above behaviour for 2160P resolution? The configuration file (main.c) is already uploaded.

 

With Regards,

Hariprasad

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Participant hariprasadb
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Registered: ‎04-23-2018

Re: Timing parameters for 4K (UHD 3840 x 2160 ) resolution

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Hi,
I traced the VTC configuration and found one more array of timing tables where 2160P related values were not added. I updated them and now " AXIS to Vid out " IP is sending out the video data continuosly.
Regards,
Hariprasad
Participant hariprasadb
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Registered: ‎04-23-2018

Re: Timing parameters for 4K (UHD 3840 x 2160 ) resolution

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Hello,

I have one more observation. I am setting the timing parameter for 1080P and 2160P. The VTC timing values/parameters are common for 60fps and 30fps. Previously, 3G-SDI output path is configured with 1 pixel per clock. Now, for 12G-SDI, it is 2 pixels per clock, so axi-strem to video is set to 2 pixels per clock (PPC). 

 

With this new setting, I am seening the AXI-strean to video output vblank as 30Hz (mapped to a test point and probed) instead of 60Hz. I am unable to figure out the reason for this behaviour.

 

My IP connections are as below. (KCU105 platform)

SDI RX (YUV 4:2:2) -> Native SDI to Video Bridge (2 PPC, probed vblank and it is 60Hz) -> Vid-to-AXI-Stream IP (PPC=2) -> VDMA (AXI-Stream width = 32 bit on both side) -> AXI-Stream to VID out (PPC=2;with VTC gen, Probed the vblank and it is 30Hz) -> SDI TX Bridge (Vid to Native SDI bridge) -> SDI TX (YUV 4:2:2)

 

 

Appreaciate your help.

 

With regards,

Hariprasad Bhat

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Moderator
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Registered: ‎11-09-2015

Re: Timing parameters for 4K (UHD 3840 x 2160 ) resolution

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Hi @hariprasadb,

 

The VTC will act only as you configure it.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Participant hariprasadb
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Registered: ‎04-23-2018

Re: Timing parameters for 4K (UHD 3840 x 2160 ) resolution

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Hi @florentw,

 

I understand the VTC behaviour now. Any suggestion regarding which IP configuration is not set properly due to which such issue may appear. VDMA or AXI-Stream to VID out?

 

With Regards,

Hariprasad Bhat

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Registered: ‎11-09-2015

Re: Timing parameters for 4K (UHD 3840 x 2160 ) resolution

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Hi @hariprasadb,

 

The timing signals (hsync, vsync, hblank and vblank) are controled only by the VTC


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Participant hariprasadb
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Registered: ‎04-23-2018

Re: Timing parameters for 4K (UHD 3840 x 2160 ) resolution

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Hello,

Very much delayed update from my side!

I have completed (3 months ago) the SDI in to out testing upto SDI-12G (4K 60fps) with following IP blocks.

SDI RX UHD SDI -> SDI Video to Native Video bridge ->Video to AXI-S IP-> Frame buffer -> Scaler (VPSS as scaler, scales to the resolution as per the output monitor))->AXI-S to Video IP -> Native Video to SDI Video bridge -> UHD SDI TX IP.

My conclusion on video design in Xilinx platform based on this activity as follows.

  •       Using VDMA IP works fine upto Full HD resolution (1080p, 60Hz) without any issue
  •       To work with higher resolution we need to use Frame buffer read & write IPs. Even all xilinx example designs for video supporting 4K comes with frame buffer IPs. I did not get any confirmation saying that VDMA doesn't support more than 1080p. 
  •       Frame buffer read & write IPs support any resolution without any issue, but need to take care the configuration sequence very carefully .
  •       Finally, always provide synchronized resets to all video IPs (as recommended by Xilinx). 

 

With regards,

Hariprasad Bhat

Moderator
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Registered: ‎11-09-2015

Re: Timing parameters for 4K (UHD 3840 x 2160 ) resolution

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HI @hariprasadb,

Thank you for sharing.

To work with higher resolution we need to use Frame buffer read & write IPs. Even all xilinx example designs for video supporting 4K comes with frame buffer IPs. I did not get any confirmation saying that VDMA doesn't support more than 1080p. 

> This is incorrect. The VDMA can be used for 4K. For example, the Displayport 1.2 example design on KCU105 or KC705 is built with the VDMA and can go up to 4K


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Participant hariprasadb
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Registered: ‎04-23-2018

Re: Timing parameters for 4K (UHD 3840 x 2160 ) resolution

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Hi @florentw,

 

Thank you for your input. I may check the VDMA for 4K after couple of months.

 

With Regards,

Hariprasad Bhat 

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