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Contributor
Contributor
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Registered: ‎03-17-2017

UHD-SDI GT cmp_gt_ctrl definition

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I'm working on a design with a single SDI transmitter using the "SMPTE UHD-SDI TX SUBSYSTEM" and "UHD-SDI GT" cores. The "UHD-SDI GT" has an input signal cmp_gt_ctrl [63:0] which I can only find any kind of definition in the RX subsystem document PG290. Table C-2 lists the description of each bit but it is lacking any indication of the polarity of these signals such as the "GT COMMON QPLL0 reset". It also doesn't say how to properly program the multi-bit signals such as "Link 0 GT LOOPBACK" which is 3bits for normal use.

Where can I find a more detailed description of these 64 bits of cmp_gt_ctrl? Do any of these signals HAVE to be toggled or can that be hard-coded to a value?

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: UHD-SDI GT cmp_gt_ctrl definition

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Hello @baf2099 

>bit 14 is for "txclk_ready" which if you search UG576 doesn't come up. Is this just meant to indicate that the GT Refclks are stable?

Yes, your undersanding is correct.
GTs should be initialized only after REFCLK is stable.
If you are using external PLL to supply GT REFCLK, you can connect PLL ready signal to bit[14], to indicate that REFCLK is good.

>If so I assume this has to be set prior to releasing the QPLL's from reset?

Yes.

Thanks & regards
Leo

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: UHD-SDI GT cmp_gt_ctrl definition

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Hello @baf2099 

Just giving some pointer.

All signals mentioned in PG290 Table C-2 is Transceiver signals.
So please find the details information on UG576 or UG578.

Thanks and regards
Leo

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Contributor
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Registered: ‎03-17-2017

Re: UHD-SDI GT cmp_gt_ctrl definition

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@karnanl based on this other forum post it would seem the ONLY bits that matter for my use case are 0, 2, & 14.

https://forums.xilinx.com/t5/Video/UHD-SDI-GT-IP-in-multilane-cases/td-p/859672

bits 0 & 2 are for QPPL0 and QPPL1 reset which UG576 indicates are active-high as seen in the "QPLL0/1 Resets" section of the doc

bit 14 is for "txclk_ready" which if you search UG576 doesn't come up. Is this just meant to indicate that the GT Refclks are stable? If so I assume this has to be set prior to releasing the QPLL's from reset?

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Re: UHD-SDI GT cmp_gt_ctrl definition

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Hello @baf2099 

>bit 14 is for "txclk_ready" which if you search UG576 doesn't come up. Is this just meant to indicate that the GT Refclks are stable?

Yes, your undersanding is correct.
GTs should be initialized only after REFCLK is stable.
If you are using external PLL to supply GT REFCLK, you can connect PLL ready signal to bit[14], to indicate that REFCLK is good.

>If so I assume this has to be set prior to releasing the QPLL's from reset?

Yes.

Thanks & regards
Leo

 

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