We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Registered: ‎10-11-2009

VDMA sync between Read and Write Channel

Hi. I have a little problem with synchronizing the frame rates between read and write channels on the VDMA. Actually there are 2 VDMA IPs in the design. It is something like:

Video Source (VTC, VideoIn to AXIS) -> (W) VDMA0 (R) -> My VideoProcessing -> (W) VDMA1 (R) -> Video output (VTC, AXIS to VideoOut)

So the configuration for VDMA0 and VDMA1 is the same - triple buffer by default: 

Write channel: Fsync - s2mm tuser, Dynamic-Master

Read channel: Fsync - none (free run), Dynamic-Slave

My VideoProcessing block operates at the frame rate delivered by VDMA0, and I am holding tuser, when I need to process some data. It is working fine. The input rate (W) of VDMA0 is correct - 60 fps, the output (R) of VDMA1 is also fine - 60 fps. They are controlled by Video Source and Output VTCs. 

But the Read channel of VDMA0 is operating as fast as it can - nearly 166 fps, this is the processing speed of VideoProcessing module at this mode, resolution and clock, so writing to VDMA1 is also so fast. This is not good, I wish to limit the Read channel on VDMA0 to the frame rate of the Write channel and process the same number of frames written to the memory. But I cant set it up correctly in free-run mode of Read channel. Is it possible at all using this configuration of the channels? Or I should provide holding tuser signal from my VideoProcessing module until new frame is written to the memory and then start new processing cycle by releasing tuser? Or generating external fsync to VDMA0 Read channel to trigger reading?

And another question directly connected to the first - may be I don't understand correctly the operations of VDMA but... in dynamic genlock configuration like above the both channels must: 

1) Write channel to not cross the position where Read channel is reading, so if the Read is slower than Write the Write must not jump over, but repeat writing at the same position until Read moves ahead and then the Write will move on the next channel (just read by Read channel and now free)?

2) Read channel to not cross the position where Write channel is writing, so if the Read channel is fast than Write then the Read must repeat the same frame until Write moves ahead and then the Read will step on the next buffer (just written by Write channel and now ready)?

So can someone help with a little theory of VDMA operations?

Thank you :)

Tags (2)
0 Kudos