We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Registered: ‎11-09-2015

Video Beginner Series 17 - Create a Video Crop IP using HLS (part 1)



This Video Beginner Series 17 shows how to create a Video Crop IP using Vivado HLS. The Video Crop IP will be created in C++ and validated using HLS Open CV library.

Video cropping is a feature which can allow use to select only a specific part of the input image to create a new image.



There are multiple User Guides to understand HLS. The main docs are UG998 - Introduction to FPGA Design with Vivado High-Level Synthesis, UG902 - Vivado Design Suite User Guide - High-Level Synthesis and UG871 - Vivado Design Suite Tutorial - High-Level Synthesis.


Note: This video series assumes that you have some knowledge in C/C++ coding.



1. Tutorial - Create a Video Crop using Vivado HLS

2. What Next?



Tutorial – Create a Video Crop IP using Vivado HLS


Note 1: This tutorial is intended to be used only with Vivado HLS 2018.1

Open the Vivado HLS project


  1. Download the tutorial files and unzip the folder

  2. Open Vivado HLS 2018.1

  3. Click on Open Project

  4. Open the project video_crop from the unzipped folder

We will start by doing a simple pass-through function.

Create the pass-through function

  1. Open the source file video_crop.cpp. We can see that it only contains the structure of the function.

  2. Add the following code to redirect the input stream to the output stream using an intermediate variable
//Top Level Function
void video_crop(AXI_STREAM& s_axis_video,AXI_STREAM& m_axis_video, int hsize_in, int vsize_in)
  ap_axiu<24, 1, 1, 1> video;

  for(int i = 0; i < vsize_in ; i ++)
         for(int j = 0; j < hsize_in ; j ++)
                 s_axis_video >> video;
                 m_axis_video << video;


  1. To test this function, we need an image as input.
    Load the image XVES_0017\src\img\in.png into the project. Click Project > Add Test Bench… and select in.png

  2. The image is now loaded under Test Bench in the project explorer. We can open it to view it:


  3. Test the function by clicking on Project > Run C simulation or on the icon 6.png directly

  4. We can verify that the output image is the same as the input image. Open out.png form the project explorer, under solution1 > csim > build > out.png


Add the cropping function

We can now add the cropping feature to output only half of the input image (only the green section).

Even if we need to output only half of the output image we still need to have to “consume” all the input image.

  1. We just need to set the output the data only when we are on the first half of the image
//Top Level Function
void video_crop(AXI_STREAM& s_axis_video,AXI_STREAM& m_axis_video, int hsize_in, int vsize_in)
  ap_axiu<24, 1, 1, 1> video;

  for(int i = 0; i < vsize_in ; i ++)
         for(int j = 0; j < hsize_in ; j ++)
                 s_axis_video >> video;

                         m_axis_video << video;


  1. Then we need to modify the test bench (video_crop_tb.cpp) to take in account that the height of the output image will be half size
  //Set output image size
  CvSize size_out;
  size_out.width = size_in.width;
  size_out.height = size_in.height/2;


  1. Run the C simulation to validate the behavior of the IP. We can see that the output image only contains the green part of the input image


Run the C Synthesis

As in the Video Beginner Series 15, we can set the directive PIPELINE to the first for loop to get better performances.

  1. Right click on the for loop in the directive window and click Insert Directive…


  1. In the Vivado HLS Directive Editor, configure as follow
    • Directive: Pipeline
    • Destination: Source File



  1. Save the source file and run C Synthesis. Click on Solution > Run C Synthesis > Active Solution or click on the icon 8.png

  2. We can now export the IP to test it in Vivado. Click on Solution > Export RTL or click on the icon  9.png

  3. In the Export RTL as IP window, leave the default settings and click OK


The IP is exported to <XVES_0017>\video_crop\solution1\impl\ip.

  1. Close Vivado HLS

In the next Beginner Video Series, we will verify the correct functionality of the IP in Vivado RTL simulation


What Next?


  • Do you have issues/questions following this Vivado Beginner Series?
    1. Search on the Xilinx forums for similar questions
    2. Create a new topic on the HLS Board or Video Board for your issue/question with the title starting with [Video Beginner Series 17] and followed by a quick description of your issue/question


  • You liked this Video Series?
    • You can give Kudos using the Kudos button  kudos.PNG
    • Make sure you are following the Xilinx Video Series topic to be informed when an new topic is published (Go to the Xilinx Video Series topic > Options > Subscribe)


Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**