UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Adventurer
Adventurer
1,419 Views
Registered: ‎08-04-2016

Video Deinterlacer design gives multiple driver nets error

Jump to solution

Hello,

 

I had a working design for processing PAL video. I then added a deinterlacer to check if the video quality improves. However, the design gives the following error:

[DRC 23-20] Rule violation (MDRV-1) Multiple Driver Nets - Net pal_vid_in_i/v_deinterlacer_0/U0/obsa5rieeogusnv5cqd has multiple drivers: pal_vid_in_i/v_deinterlacer_0/U0/obsivmmh/G, pal_vid_in_i/processing_system7_0/inst/PS7_i/MAXIGP0WSTRB[0], pal_vid_in_i/processing_system7_0/inst/PS7_i/MAXIGP0WSTRB[1].

 

The cpu_interface is attached to an AXI interconnect. The design is attached.Capture.PNG

 

What could the problem be? 

Also, why does Vivado not prompt with Run Connection Automation for the deinterlacer?

 

Thanks,

Rajat Rao

Tags (1)
0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
1,732 Views
Registered: ‎11-09-2015

Re: Video Deinterlacer design gives multiple driver nets error

Jump to solution

Hi @rajatrao,

 

First you need to be aware that the deinterlacer is a discontinued IP and there is no official support for it. For new designs, you might want to use the Video Processing Subsystem (VPSS) IP.

 

Then, on you screenshot you are not showing the source of video_in which seems to have the issue. Please share a IPI screenshot and a synthesized design showing the multiple drivers.

 

Best Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
8 Replies
Moderator
Moderator
1,733 Views
Registered: ‎11-09-2015

Re: Video Deinterlacer design gives multiple driver nets error

Jump to solution

Hi @rajatrao,

 

First you need to be aware that the deinterlacer is a discontinued IP and there is no official support for it. For new designs, you might want to use the Video Processing Subsystem (VPSS) IP.

 

Then, on you screenshot you are not showing the source of video_in which seems to have the issue. Please share a IPI screenshot and a synthesized design showing the multiple drivers.

 

Best Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Adventurer
Adventurer
1,371 Views
Registered: ‎08-04-2016

Re: Video Deinterlacer design gives multiple driver nets error

Jump to solution

Hi @florentw,

 

I started a design based on vpss in de-int mode only. Could you tell me how best to configure it. The example design in the SDK install folder configures the entire system. Is there an easier way of simply configuring the deinterlacer through the functions found in xv_deinterlacer.h?

 

Thanks,

Rajat Rao

0 Kudos
Moderator
Moderator
1,367 Views
Registered: ‎11-09-2015

Re: Video Deinterlacer design gives multiple driver nets error

Jump to solution

Hi @rajatrao,

 

The example design is also doing configuration for deinterlacer only if you look at it carrefuly


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Adventurer
Adventurer
684 Views
Registered: ‎05-28-2018

Re: Video Deinterlacer design gives multiple driver nets error

Jump to solution

I'm running into this VERY same issue, except it is when I connect the Deinterlacer core to a Microblaze.  I looked into this and found something interesting.

The Net that Vivato is complaining about:

[DRC MDRV-1] Multiple Driver Nets: Net FPGA3Core/v_deinterlacer_1/U0/obsa5rieeogusnv5cqd has multiple drivers: FPGA3Core/v_deinterlacer_1/U0/obsivmmh/G

is a GROUND net!   Why in the world is Vivato connecting this internal net to byte_enables (Q ouput) from the Microblaze core??

Is there something WRONG with this IP core??

It may be discontinued for Vivato versions 2018+, but I'm still using 2017.4 and trying to complete a product based on this stuff!!

0 Kudos
Adventurer
Adventurer
645 Views
Registered: ‎05-28-2018

Re: Video Deinterlacer design gives multiple driver nets error

Jump to solution

Additional:It seems that for the AXI4-Lite Slave interface on the Deinterlacer, s_axi_bresp[1:0] and s_axi_rresp[1:0] are tied to ground. These are the .../G net that the error calls out - Ground.

Deinterlacer-AXI4-Lite_Slave.png
0 Kudos
Adventurer
Adventurer
642 Views
Registered: ‎05-28-2018

Re: Video Deinterlacer design gives multiple driver nets errorI

Jump to solution

I examined the AXI interface between the AXI_Interconnect IP and the Deinterlacer, and when I hooked everything up manually, the Output Product Generator puked. I eliminated most connections and just left the M07_AXI_rresp[1:0] and M07_AXI_bresp[1:0] connected manually, and the Generator puked again saying it could not find connections to M07_AXI_bresp[1:0] -    Huh???

[BD 41-99] Failed to find BusTerm object /axi_interconnect_0/M07_AXI_bresp

I think this may be the result of the s_axi_rresp[1:0] and s_axi_bresp[1:0] outputs getting tied together and grounded.

When i eliminated the M07_AXI_bresp[1:0] manual connection, the Generator produced all the output products and performed the Out of Context Synthesis. However, that then caused the multiple driver error on the AXI_bresp[1:0] INPUTS to the AXI_Interconnect!!!

This REALLY feels like a bug in the Block Diagram Generator in Vivato!! 

0 Kudos
Adventurer
Adventurer
621 Views
Registered: ‎05-28-2018

Re: Video Deinterlacer design gives multiple driver nets errorI

Jump to solution

Workaround:

I pulled the s_axi_bresp[1:0] of the Deinterlacer IP out to a port in the block diagram and orphaned it.

Problem solved.

0 Kudos
Adventurer
Adventurer
573 Views
Registered: ‎05-28-2018

Re: Video Deinterlacer design gives multiple driver nets errorI

Jump to solution

Well, I spoke too soon. This issue keeps creeping back into my design. occasionally, it goes away for some unknown reason, but then creeps back.

Something about the Deinterlacer IP is bringing this to the surface. Just thinking it through, if an encrypted core wants to connect two outputs to GND, it really should be able to do that w/out any ramifications. I think there is something else wrong that this core is bringing out!

Still investigating.