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Adventurer
Adventurer
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Registered: ‎05-28-2018

Video IP blocks and the Video Processing Subsystem - Chroma Resampler, Deinterlacer, Colorspace converter

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So, I've been wrestling with some issues regarding these particular Xilinx Video IP blocks, and I decided to reach out to the Forums to get some answers.

Initially, I was using the Chroma Resampler IP and RGB2YCrCb/YCrCb2RGB Colorspace Converter IP blocks in a design. I was able to implement these and get the designs to work, but then I needed to implement Deinterlacing. I immediately had weird issues with the Deinterlacer IP (AXI-Byte Enbles getting redefined from inputs to outputs and causing multiple-drivers on the GND node,) and I started looking to the forums for help. I found an article where Xilinx suggested the designer look at the Video Processing Subsystem for this functionality, so I did as well. I was please to find out that you could "trim" or focus the Video Processing Subsystem to separate functions like chroma-resamplling, Color Space Conversion and Deinterlacing, but I ran into the following issues.

* First, in the Documentation for the Video Processing Subsystem IP (pg231-v_proc-ss.pdf) there is LITTLE or NO register descriptions of the IP that is contained in this Subsystem. As opposed to the docs for the "deprecated/deprecating" IP like the Deinterlacer (pg017-v_deinterlacer.pdf,) the Chroma Resampler (pg012_v_cresample.pdf,) or either of the Color Space Converter IP blocks (pg013_v_RGB2YCrCb.pdf or pg014_v_YCrCb2RBG.pdf), which do a GREAT job of documenting registers for these IPs, the Video Processing Subsystem has NONE.

Q: Where do I go for that documentation? (Please don't tell me APIs, because there is no bit by bit register description there.)

* Second, I was able to take one of the Video Beginner Series tutorials, especially - Video Beginner Series 8: Debugging the AXI4-Stream to Video Out IP (lab 1,) and add the Chroma Resampler(v_cresample) and RGB2YCrCb (v_RBG2YCrCb) IP blocks and simulate going from RBG to 4:2:2 YuV and out the AXI4S_Video_Out block successfully! Which helped me to successfully implement the IP in hardware.

* Now, I try and replace the Chroma Resample in that "design" with a block from the Video Processing Subsystem, and the FIRST thing I run into, is that the output from the Chroma Resampler (4:4:4-->4:2:2) instead of being a 16-bit databus as defined in the overall AXI Video IP User's Guide (ug934,) it's still a 24-bit bus -- COMPLETELY different than the deprecated v_cresample IP. ???

* Also, when I replace the v_cresample IP with the Chroma Resampler VPSS block, I get NO data through the block. My first thought was that I needed to START the VPSS block. I DID look at the API's for the VPSS and it wrote a 1b'0' to the Control Register, so I had to implement a AXI_CrossBar with 17-bit addressing to get the TPG and VPSS on their own write-able 64K page, and after the TPG was setup and started, I started the VPSS - Still no Go.

Q: What am I doing wrong???

Lab1_VPSS.png
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Video IP blocks and the Video Processing Subsystem - Chroma Resampler, Deinterlacer, Colorspace converter

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@gcsimmonsjr wrote:

So, I've been wrestling with some issues regarding these particular Xilinx Video IP blocks, and I decided to reach out to the Forums to get some answers.

Initially, I was using the Chroma Resampler IP and RGB2YCrCb/YCrCb2RGB Colorspace Converter IP blocks in a design. I was able to implement these and get the designs to work, but then I needed to implement Deinterlacing. I immediately had weird issues with the Deinterlacer IP (AXI-Byte Enbles getting redefined from inputs to outputs and causing multiple-drivers on the GND node,) and I started looking to the forums for help. I found an article where Xilinx suggested the designer look at the Video Processing Subsystem for this functionality, so I did as well. I was please to find out that you could "trim" or focus the Video Processing Subsystem to separate functions like chroma-resamplling, Color Space Conversion and Deinterlacing, but I ran into the following issues.

* First, in the Documentation for the Video Processing Subsystem IP (pg231-v_proc-ss.pdf) there is LITTLE or NO register descriptions of the IP that is contained in this Subsystem. As opposed to the docs for the "deprecated/deprecating" IP like the Deinterlacer (pg017-v_deinterlacer.pdf,) the Chroma Resampler (pg012_v_cresample.pdf,) or either of the Color Space Converter IP blocks (pg013_v_RGB2YCrCb.pdf or pg014_v_YCrCb2RBG.pdf), which do a GREAT job of documenting registers for these IPs, the Video Processing Subsystem has NONE.

Q: Where do I go for that documentation? (Please don't tell me APIs, because there is no bit by bit register description there.)

[Florent] - Well...Sorry...But I will tell you...APIs... ;)

We do not provide the register map to the users for the VPSS. The user is expected to use the APIs. The VPSS is a complex IP and allowing the user to control it through the register map would lead to many issues.

All the APIs should be clearly documented in the driver documentation

* Second, I was able to take one of the Video Beginner Series tutorials, especially - Video Beginner Series 8: Debugging the AXI4-Stream to Video Out IP (lab 1,) and add the Chroma Resampler(v_cresample) and RGB2YCrCb (v_RBG2YCrCb) IP blocks and simulate going from RBG to 4:2:2 YuV and out the AXI4S_Video_Out block successfully! Which helped me to successfully implement the IP in hardware.

* Now, I try and replace the Chroma Resample in that "design" with a block from the Video Processing Subsystem, and the FIRST thing I run into, is that the output from the Chroma Resampler (4:4:4-->4:2:2) instead of being a 16-bit databus as defined in the overall AXI Video IP User's Guide (ug934,) it's still a 24-bit bus -- COMPLETELY different than the deprecated v_cresample IP. ???

[Florent] - First, I am glad you read my video series. It is always good to see that it is helpful for the community.

The VPSS still as a 24 bit input because it can do both way (422 -> 444 and 444 -> 422). If you are only doing 444->422 you just have to put and AXI-Subset converter as mentioned in my Video Series 12.

* Also, when I replace the v_cresample IP with the Chroma Resampler VPSS block, I get NO data through the block. My first thought was that I needed to START the VPSS block. I DID look at the API's for the VPSS and it wrote a 1b'0' to the Control Register, so I had to implement a AXI_CrossBar with 17-bit addressing to get the TPG and VPSS on their own write-able 64K page, and after the TPG was setup and started, I started the VPSS - Still no Go.

Q: What am I doing wrong???

[Florent] - Yes you are correct you need to start the VPSS (using the APIs). You might want to refer to the example design to know the exact flow SDK\2018.3\data\embeddedsw\XilinxProcessorIPLib\drivers\vprocss_v2_5\examples.

You will see that it uses the following API: XVprocSs_SetSubsystemConfig(VpssPtr);

 


Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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11 Replies
Moderator
Moderator
955 Views
Registered: ‎11-09-2015

Re: Video IP blocks and the Video Processing Subsystem - Chroma Resampler, Deinterlacer, Colorspace converter

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@gcsimmonsjr wrote:

So, I've been wrestling with some issues regarding these particular Xilinx Video IP blocks, and I decided to reach out to the Forums to get some answers.

Initially, I was using the Chroma Resampler IP and RGB2YCrCb/YCrCb2RGB Colorspace Converter IP blocks in a design. I was able to implement these and get the designs to work, but then I needed to implement Deinterlacing. I immediately had weird issues with the Deinterlacer IP (AXI-Byte Enbles getting redefined from inputs to outputs and causing multiple-drivers on the GND node,) and I started looking to the forums for help. I found an article where Xilinx suggested the designer look at the Video Processing Subsystem for this functionality, so I did as well. I was please to find out that you could "trim" or focus the Video Processing Subsystem to separate functions like chroma-resamplling, Color Space Conversion and Deinterlacing, but I ran into the following issues.

* First, in the Documentation for the Video Processing Subsystem IP (pg231-v_proc-ss.pdf) there is LITTLE or NO register descriptions of the IP that is contained in this Subsystem. As opposed to the docs for the "deprecated/deprecating" IP like the Deinterlacer (pg017-v_deinterlacer.pdf,) the Chroma Resampler (pg012_v_cresample.pdf,) or either of the Color Space Converter IP blocks (pg013_v_RGB2YCrCb.pdf or pg014_v_YCrCb2RBG.pdf), which do a GREAT job of documenting registers for these IPs, the Video Processing Subsystem has NONE.

Q: Where do I go for that documentation? (Please don't tell me APIs, because there is no bit by bit register description there.)

[Florent] - Well...Sorry...But I will tell you...APIs... ;)

We do not provide the register map to the users for the VPSS. The user is expected to use the APIs. The VPSS is a complex IP and allowing the user to control it through the register map would lead to many issues.

All the APIs should be clearly documented in the driver documentation

* Second, I was able to take one of the Video Beginner Series tutorials, especially - Video Beginner Series 8: Debugging the AXI4-Stream to Video Out IP (lab 1,) and add the Chroma Resampler(v_cresample) and RGB2YCrCb (v_RBG2YCrCb) IP blocks and simulate going from RBG to 4:2:2 YuV and out the AXI4S_Video_Out block successfully! Which helped me to successfully implement the IP in hardware.

* Now, I try and replace the Chroma Resample in that "design" with a block from the Video Processing Subsystem, and the FIRST thing I run into, is that the output from the Chroma Resampler (4:4:4-->4:2:2) instead of being a 16-bit databus as defined in the overall AXI Video IP User's Guide (ug934,) it's still a 24-bit bus -- COMPLETELY different than the deprecated v_cresample IP. ???

[Florent] - First, I am glad you read my video series. It is always good to see that it is helpful for the community.

The VPSS still as a 24 bit input because it can do both way (422 -> 444 and 444 -> 422). If you are only doing 444->422 you just have to put and AXI-Subset converter as mentioned in my Video Series 12.

* Also, when I replace the v_cresample IP with the Chroma Resampler VPSS block, I get NO data through the block. My first thought was that I needed to START the VPSS block. I DID look at the API's for the VPSS and it wrote a 1b'0' to the Control Register, so I had to implement a AXI_CrossBar with 17-bit addressing to get the TPG and VPSS on their own write-able 64K page, and after the TPG was setup and started, I started the VPSS - Still no Go.

Q: What am I doing wrong???

[Florent] - Yes you are correct you need to start the VPSS (using the APIs). You might want to refer to the example design to know the exact flow SDK\2018.3\data\embeddedsw\XilinxProcessorIPLib\drivers\vprocss_v2_5\examples.

You will see that it uses the following API: XVprocSs_SetSubsystemConfig(VpssPtr);

 


Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
946 Views
Registered: ‎05-28-2018

Re: Video IP blocks and the Video Processing Subsystem - Chroma Resampler, Deinterlacer, Colorspace converter

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I appreciate your replying so fast!  Actually, Thank you for the Video Series, it has been VERY helpful. I continue to learn from it. I will look up what you suggested.

However, I'd really like to do what I did before (attached schematic from previous post,) and verify the behavior of the IP with the Lab1 you provided for the Video Out IP core.

Is there a way to write verilog commands in the tb_AXI4S_to_Vid_Out.sv in order to start the VPSS?

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Video IP blocks and the Video Processing Subsystem - Chroma Resampler, Deinterlacer, Colorspace converter

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Hi @gcsimmonsjr,

No the VPSS does not support simulation (because you need to use the drivers). Actually, this is the reason why I used the old IPs instead of the VPSS (while writing that you should use the VPSS).

You could workaround that by simulating the VPSS with a microblaze + the .elf file with the application but I would not recommend it as it will be complex and really slow.

Usually, we are recommending the user to try directly on-board because we are getting to high resolutions which would require a really long simulation time. So it is easier to just run on board directly.

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
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Registered: ‎05-28-2018

Re: Video IP blocks and the Video Processing Subsystem - Chroma Resampler, Deinterlacer, Colorspace converter

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OK. I found the same thing. I usually knock the resolution down to 480p or 480i for simulation.

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Adventurer
Adventurer
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Registered: ‎05-28-2018

Re: Video IP blocks and the Video Processing Subsystem - Chroma Resampler, Deinterlacer, Colorspace converter

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Additional question. I'm reading your Video Beginner Series 12 section, and I noticed that sometimes you are changing the TUSER bits, and I'm not sure if I understand why.

For example, if I'm interfacing a Vid_In_AXI4S block, 10-bit RGB, to the VPSS, the AXI4S Master is video_tdata[23:0], and the VPSS is Slave video_tdata[31:0]. If I use an axis_data_width_converter, how do I know what to set the TUSER bits to?  I tried turning this to AUTO, but I got the following Warning:

[xilinx.com:ip:axis_dwidth_converter:1.1-1] /axis_dwidth_converter_0Slave interface TUSER_WIDTH (1) is not an integer multiple of number of slave interface TDATA_NUM_BYTES (3). TUSER_BITS_PER_BYTE forced to 0.

Is this expected and OK?

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Moderator
Moderator
904 Views
Registered: ‎11-09-2015

Re: Video IP blocks and the Video Processing Subsystem - Chroma Resampler, Deinterlacer, Colorspace converter

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Hi @gcsimmonsjr,

Video IPs are only using a single bit for the tuser. I would recommend to force it to be a single bit to match with the IPs.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Adventurer
Adventurer
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Registered: ‎05-28-2018

Re: Video IP blocks and the Video Processing Subsystem - Chroma Resampler, Deinterlacer, Colorspace converter

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Just to Double-Check.  The AXIS Data-Width Converter IP says "TUSER bits per byte."

Is this a misnomer, and it should read TUSER bits per transfer (NUM_BYTES long) ?

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: Video IP blocks and the Video Processing Subsystem - Chroma Resampler, Deinterlacer, Colorspace converter

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Hi @gcsimmonsjr,

No bit per byte is correct. This IP will configure the tuser width depending on the width of your tdata (in byte).

Regards


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Adventurer
Adventurer
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Registered: ‎05-28-2018

Re: Video IP blocks and the Video Processing Subsystem - Chroma Resampler, Deinterlacer, Colorspace converter

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OK, I think I get it now. Apologies for my thick-headedness. I'm from an old 8-bit S/W background, and when I see BYTE, I think 8-bits per BYTE, 4-bits per NIBBLE - and WORDs vary from 16-bits to 256-bits, in all shapes and sizes.

I re-read the AXI UG761, and I know understand that the TUSER bits are meant for side-band communication, and are usually specified as a TUSER bus, with its width in bits. I was confusing this as a bit per BYTE of TDATA (3 Bytes of TDATA ==> 3-bits of TUSER.) Now, I understand they are really unrelated.

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Observer sabiya
Observer
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Registered: ‎07-26-2019

Re: Video IP blocks and the Video Processing Subsystem - Chroma Resampler, Deinterlacer, Colorspace converter

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Hi,

I implemented a video processing subsystem ip blocks on zcu102. But, i need frame rate conversion from the input is 24fps and my output want to set 60fps. So, i need a help how it convert.

Thanks.

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Moderator
Moderator
248 Views
Registered: ‎11-09-2015

Re: Video IP blocks and the Video Processing Subsystem - Chroma Resampler, Deinterlacer, Colorspace converter

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Hi @sabiya 

How many times will you ask this question? I already answered it.

If you do not have enough knowledge to do your own design then you should work with a design services company. Nobody will do the design for you on the forums...


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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