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Visitor zachkf
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Registered: ‎01-10-2019

Video Phy Configuration for Displayport 1.4 Subsystems

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Hello,

I'm implementing a testbench of the Displayport 1.4 Subsystem, and Video PHY Controller on a Kintex 7 Ultrascale device (xcku115-flvf1924-2-i). For test purposes the TX out lines are connected to the RX in lines (I'm intending to feed test data through the TX and verify it on the output of the RX). The intention is to not use linux for control, but implement RX/TX control in hardware.

Despite using the example design as a reference, and following the reset/initialization procedures provided in PG230, PG300, and PG233 for RX, and PG230, PG299, and PG199 for TX, the TX and RX components are not performing a handshake through the AUX channel despite the HPD signal being high.

The issue seems to be related to the lnk_clk being stuck low on the TX (which prevents the TX from detecting the HPD high I believe). To me this would imply that the reference clock isn't selected correctly, however the documentation isn't clear about how to select a reference clock through the register (register 0x0010, PG230 page 22). Currently I'm setting them as follows:

VID_PHY_TX = 0x88000FFF

VID_PHY_RX = 0x88000FFF

My initialization procedure for RX is as follows:

/*
                        PG233 page 56 Initialization procedure + addittional changes based on documentation:

                        Step | Component   | Register | Value      | Description
                        -----|-------------|----------|------------|--------------------
                        1    | DisplayPort | 0x000C   | 0x0        | Disable DTG
                        2    | DisplayPort | 0x0000   | 0x0        | Disable the main link
                        3    | Video Phy   | 0x0014   | 0x7        | PLL Resets
                        4    | Video Phy   | 0x0024   | 0xFFFFFFFF | GT Resets (DP RX, & PHY)
                        5    | DisplayPort | 0x0004   | 0x1818     | Set AUX Clock Divider
                        X    | DisplayPort | 0x0214   | 0x1445     | Set RX Voltage Swing // I'm going to be skipping this temporarily as I can assume the defaults are correct for now
                        6    | Video Phy   | 0x0010   | 0x88000112 | Set reference clock for link
                        7    | DisplayPort | 0x021c   | 0x1388     | Configure tDLOCK
                        8    | DisplayPort | 0x0300   | 0x0        | Disable Audio
                        9    | Video Phy   | 0x0014   | 0x0        | PLL Un-Reset
                        10   | Video Phy   | 0x0024   | 0x0        | GT Un-Reset (CPLL, DP RX, & PHY)
                        11   | Video Phy   | 0x0018   | Rx1F       | Wait for PHY CPLL lock ready
                        12   | Video Phy   | 0x0028   | Rx07070707 | Wait for PHY reset done
                        13   | DisplayPort | 0x0000   | 0x1        | Enable DisplayPort Link
                        14   | DisplayPort | 0x000C   | 0x1        | Enable DTG
                        15   | DisplayPort | 0x001C   | 0x181      | Apply soft reset
                        16   | DisplayPort | 0x001C   | 0x000      | Remove soft reset

                        - R => Read until specified value is found, then continue
*/

My initialization procedure for TX is as follows:

/*
                        PG199 page 53 Initialization procedure + Changes based on documentation:

                        Step | Component   | Register | Value      | Description
                        -----|-------------|----------|------------|--------------------
                        1    | Video Phy   | 0x0014   | 0x7        | Place PHY PLL into reset
                        2    | Video Phy   | 0x001C   | 0xFFFFFFFF | Place PHY DP TX into reset
                        3    | DisplayPort | 0x0080   | 0x0        | Disable the main link
                        4    | DisplayPort | 0x010C   | 0x1818     | Set the AUX clock divider
                        5    | DisplayPort | 0x0004   | 0x4        | Set the number of lanes to 4
                        6    | DisplayPort | 0x0000   | 0x1E       | Set the main link rate to 8.1Gb/s
                        7    | DisplayPort | 0x0090   | 0x1        | Enable video packing in the lnk_clk domain
                        8    | Video Phy   | 0x0010   | 0x88000112 | Set reference clock for link
                        9    | Video Phy   | 0x0014   | 0x0        | Take Phy PLL out of reset
                        10   | Video Phy   | 0x001C   | 0x0        | Take Phy DP TX out of reset
                        11   | Video Phy   | 0x0018   | Rx1F       | Wait for PHY CPLL lock ready
                        12   | Video Phy   | 0x0020   | Rx07070707 | Wait for PHY reset done
                        13   | DisplayPort | 0x0080   | 0x1        | Enable the main link
                        14   | DisplayPort | 0x001C   | 0x8F       | Apply soft reset
                        15   | DisplayPort | 0x001C   | 0x00       | Remove soft reset

                        - R => Read until specified value is found, then continue
*/

I'm using an AXI4L VIP (PG267) to write to the registers currently.

If there is any guidence I could get on the restart/initialization procedure, or better documentation/examples/references that would be dandy.

Cheers,

Zach KF

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Moderator
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468 Views
Registered: ‎11-09-2015

Re: Video Phy Configuration for Displayport 1.4 Subsystems

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Hi @zachkf,

Just to clarify. The example application is for baremetal application not for Linux.

In fact there are no Linux drivers for the DP subsystems. What ypu find is for baremetal application (i.e. No OS - but with a processor).

From my point of view, you should just start with the GT control. The UG576  should contains what you need. However, I am not sure about what is needed in simulation and how much simulation time you need to wait between each steps


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
485 Views
Registered: ‎11-09-2015

Re: Video Phy Configuration for Displayport 1.4 Subsystems

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Hi @zachkf,

  • Kindly note that simulation is not supported for the Video PHY and the Displayport 1.4 IP as mentioned in its Product Guide. You will not get any support from Xilinx on this topic (but you could still get support from the community). I would recommend to test the IP directly in HW.
  • Also in your code you are refering to the PG for the DP1.2 IP while you said you are using the DP1.4 IP. You might want to use the correct PG
  • Finally, the best way to know how to configure the IPs is to check the example application generated in SDK

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor zachkf
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Registered: ‎01-10-2019

Re: Video Phy Configuration for Displayport 1.4 Subsystems

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Hi @florentw,

  • I understand that simulation is not supported, but the reset/initialization should be the same procedure for Simulation, Synthesis, and Implementation. While I'll be testing in HW ASAP, I don't see a reason why the reset/initialization procedure couldn't be tested in simulation.
  • The DP 1.2 (PG233) is referenced as there is no equivelent initialization procedure available in the DP 1.4 (PG300) documentation. PG300 has "recomendations" on page 40, However these alone don't initialize the DP 1.4 IP. The initialization procedure is equivalent in PG299 and PG199 for TX, I used the DP 1.4 documentation (PG299) for my initialization of TX.
  • The example design is based around using the IP in the context of a Linux environment where software/drivers manage the initialization of the DP 1.4 connection. As this is a HW only implementation for DP 1.4, the example design isn't particularly useful.

I have also refered to the [Linux driver](https://github.com/Xilinx/embeddedsw/tree/fb647e6b4c00f5154eba52a88b948195b6f1dc2b/XilinxProcessorIPLib/drivers/dp14/src) for information, however C/drivers are not my area of expertise, so getting information out is difficult.

If I could just get more information on configuring the reference clocks for Video Phy, past what UG576 and PG230 offer, that would probably get me to a working design.

Cheers,

Zach KF

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Moderator
Moderator
469 Views
Registered: ‎11-09-2015

Re: Video Phy Configuration for Displayport 1.4 Subsystems

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Hi @zachkf,

Just to clarify. The example application is for baremetal application not for Linux.

In fact there are no Linux drivers for the DP subsystems. What ypu find is for baremetal application (i.e. No OS - but with a processor).

From my point of view, you should just start with the GT control. The UG576  should contains what you need. However, I am not sure about what is needed in simulation and how much simulation time you need to wait between each steps


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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Visitor zachkf
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443 Views
Registered: ‎01-10-2019

Re: Video Phy Configuration for Displayport 1.4 Subsystems

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@florentw I'll see what UG576 has to offer.

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