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Registered: ‎11-24-2016

[Video Series 26] - Question about the memory use

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@florentw 

Q1: In your Series 26, example 2(picture in picture), there is a ‘offset’ value. I change the example into my project, I found the offset number must at least 8 times. My VDMA axi-data-width is 128bit(16Byte), burst length is 4, DDR write byte is aligned with 4Byte(int type). I do not understand Why it is 8 times, not 4 times.

I think the offset = (frame_width*line_number+pixel_number)*pixel_byte_number.

 

Q2:I use zcu102 board, on board PS DDR has 4G size, but in my hardware design address editorHP0_DDR_LOW max size is 2G, HP0_DDR_HIGH max size is 32G, Can I setting that I can use the all 4G memory?

And the generated lscript.ld file, The default setting, there are two ddr memory. psu_ddr_0_MEM_0 size is 2G. psu_ddr_1_MEM_0 size is also 2G.

Does psu_ddr_0_MEM_0 correspond to HP0_DDR_LOW?

Does psu_ddr_1_MEM_0 correspond to HP0_DDR_HIGH?

 

1.png

2.png

 

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Registered: ‎11-09-2015

Re: [Video Series 26] - Question about the memory use

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HI @luoyanghero 

Again, this is mentioned on the note of my video series that the offset should be a multiple axifull_width_byte. My code is not checking if the value is correct as I am using direct registers programing


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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View solution in original post

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Registered: ‎11-09-2015

Re: [Video Series 26] - Question about the memory use

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HI @luoyanghero 

Note that I have moved your question to a new topic as this is a different question. Please keep one question/topic.


@luoyanghero wrote:

@florentw 

Q1: In your Series 26, example 2(picture in picture), there is a ‘offset’ value. I change the example into my project, I found the offset number must at least 8 times. My VDMA axi-data-width is 128bit(16Byte), burst length is 4, DDR write byte is aligned with 4Byte(int type). I do not understand Why it is 8 times, not 4 times.

I think the offset = (frame_width*line_number+pixel_number)*pixel_byte_number.

[Florent]- This is answered in the note in the example 1:

Note: In this example, the offset needs to be a multiple of the memory map data width bytes (32-bits) as “Allow Unaligned Transfers” is not enable in the AXI VDMA IP configuration.

If you do not have the “Allow Unaligned Transfers” option enabled you need to be aligned with the memory map width which is 32-bits or 8bytes. So what you are seeing makes sense

Q2:I use zcu102 board, on board PS DDR has 4G size, but in my hardware design address editorHP0_DDR_LOW max size is 2G, HP0_DDR_HIGH max size is 32G, Can I setting that I can use the all 4G memory?

[Florent]- You need to match what you have in your HW. The address editor shows you what is possible with the ZU+ (if it was with another board with different DDR). You need to use the default settings which is 2G and 2G

And the generated lscript.ld file, The default setting, there are two ddr memory. psu_ddr_0_MEM_0 size is 2G. psu_ddr_1_MEM_0 size is also 2G.

Does psu_ddr_0_MEM_0 correspond to HP0_DDR_LOW?

[Florent] - Yes

Does psu_ddr_1_MEM_0 correspond to HP0_DDR_HIGH?

[Florent] - Yes

1.png

2.png

 


 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-24-2016

Re: [Video Series 26] - Question about the memory use

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@florentw 32bit is 4byte, not 8byte.  My env must need 8byte aligned.

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Re: [Video Series 26] - Question about the memory use

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Hi @luoyanghero 

Yes sorry my bad. But at then end what is the address you are starting to read at? This is the one which needs to be aligne to 32-bit.


Florent
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Re: [Video Series 26] - Question about the memory use

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@florentw  My start address is aligned with 32bit. I tested 'offset = 0x6480C;//(1080*127+60)*3;' 4 times, bad.

 

My config is as following:

UINTPTR g_vdmaDataBaseAddr1 = 0x10000000;
UINTPTR g_vdmaDataBaseAddr2 = 0x11800000;
UINTPTR g_vdmaDataBaseAddr3 = 0x13000000;
#define FRM_WIDTH  1080
#define FRM_HEIGHT 2340
#define SUBFRM_WIDTH  800
#define SUBFRM_HEIGHT 1600
...
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x30, 0x8B);//0x30: S2MM VDMA Control Register; GenLock Enable
    //Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x30, 0x1003308B);//0x30: S2MM VDMA Control Register; GenLock Enable
    //Offset to center the pattern on the buffer
    //offset = 0x65580;//(1080*128+128)*3 128Line, 128 pix, 3 Byte; ok
    //offset = 0x654C0;//(1080*128+64)*3; ok
    //offset = 0x65460;//(1080*128+32)*3; 32 times ok
    //offset = 0x65490;//(1080*128+48)*3; 16 times ok
    //offset = 0x6480C;//(1080*127+60)*3; 4 times bad
    //offset = 0x64815;//(1080*127+63)*3; 1 times bad
    offset = 0x654A8;//(1080*128+56)*3; 8 times ok. at list 8times, why

    //S2MM Start Address 1
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xAC, g_vdmaDataBaseAddr1+offset);
    //S2MM Start Address 2
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xB0, g_vdmaDataBaseAddr2+offset);
    //S2MM Start Address 3
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xB4, g_vdmaDataBaseAddr3+offset);
    //S2MM Frame delay / Stride register
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA8, FRM_WIDTH*3);//0xA8: S2MM Frame Delay and Stride (Byte)
    // S2MM HSIZE register
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA4, SUBFRM_WIDTH*3);
    // S2MM VSIZE register
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA0, SUBFRM_HEIGHT);

    /* Configure the Read interface (MM2S)*/
    // MM2S Control Register
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x00, 0x8B);//0x00: MM2S VDMACR Register; GenLock Enable
    //Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x00, 0x1003308B);//0x00: MM2S VDMACR Register; GenLock Enable
    // MM2S Start Address 1
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x5C, g_vdmaDataBaseAddr1);
    // MM2S Start Address 2
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x60, g_vdmaDataBaseAddr2);
    // MM2S Start Address 3
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x64, g_vdmaDataBaseAddr3);
    // MM2S Frame delay / Stride register
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x58, FRM_WIDTH*3);//0x58: MM2S Frame Delay and Stride (Byte)
    // MM2S HSIZE register
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x54, FRM_WIDTH*3);//0x54: Horizontal size (Byte).
    // MM2S VSIZE register
    Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x50, FRM_HEIGHT);//0x50: Vertical Size

 

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Re: [Video Series 26] - Question about the memory use

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Hi @luoyanghero 

Offset 0x64815 is expected to fail because you will not be 32-bits aligned. You final address needs to end by 0x0, 0x4, 0x8 or 0xC.

I am not sure why 0x6480C is failing but it might be a different issue. One way to check is to allow the unaligned transferts and see if that makes it work


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-24-2016

Re: [Video Series 26] - Question about the memory use

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@florentw I use intterrupt-example to test my design, It shows me write-error. I have opened '-DDEBUG' option. I want to get more debug infomation. Is there some other way to help me find the error?

I find another topic. It has 'DEBUG_MODE' code, and can diff write-read data one by one. Where can I get the 'DEBUG_MODE' example code?

https://forums.xilinx.com/t5/%E5%B5%8C%E5%85%A5%E5%BC%8F%E8%BD%AF%E4%BB%B6%E5%BC%80%E5%8F%91/SDK-vdma%E9%97%AE%E9%A2%98/td-p/879239

Other than this, I will try unaligned.

The following are my VDMA IP config settings. I changed some property for bebug(CONFIG.c_enable_all=1) and interrupt(CONFIG.c_enable_mm2s_frmstr_reg=1), default setting c_enable_mm2s_frmstr_reg=0, but interrupt need c_enable_mm2s_frmstr_reg=1, why?

 

2.jpg3.jpg4.jpg1.jpg

intterrupt-example code:

/******************************************************************************
*
* Copyright (C) 2012 - 2018 Xilinx, Inc.  All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/
/*****************************************************************************/
/**
 *
 * @file xaxivdma_example_intr.c
 *
 * This example demonstrates how to use the AXI Video DMA with other video IPs
 * to do video frame transfers. This example does not work by itself. It needs
 * two other Video IPs, one for writing video frames to the memory and one for
 * reading video frames from the memory.
 *
 * To see the debug print, you need a Uart16550 or uartlite in your system,
 * and please set "-DDEBUG" in your compiler options. You need to rebuild your
 * software executable.
 *
 * @note
 * The values of DDR_BASE_ADDR and DDR_HIGH_ADDR should be as per the HW system.
 *
 * <pre>
 * MODIFICATION HISTORY:
 *
 * Ver   Who  Date     Changes
 * ----- ---- -------- -------------------------------------------------------
 * 1.00a jz   07/26/10 First release
 * 1.01a jz   09/26/10 Updated callback function signature
 * 2.00a jz   12/10/10 Added support for direct register access mode, v3 core
 * 2.01a rvp  01/22/11 Renamed the example file to be consistent
 * 		       Added support to the example to use SCU GIC interrupt
 *		       controller for ARM, some functions in this example have
 *		       changed.
 *       rkv  03/28/11 Updated to support for frame store register.
 * 3.00a srt  08/26/11 Added support for Flush on Frame Sync Feature.
 * 4.00a srt  03/06/12 Modified interrupt support for Zynq.
 * 4.02a srt  09/25/12 Fixed CR 677704
 *		       Description - Arguments misused in function
 *                     XAxiVdma_IntrEnable().
 * 4.03a srt  03/01/13 Updated DDR base address for IPI designs (CR 703656).
 * 6.2   ms   01/23/17 Modified xil_printf statement in main function to
 *                     ensure that "Successfully ran" and "Failed" strings
 *                     are available in all examples. This is a fix for
 *                     CR-965028.
 * 6.5   rsp  12/01/17 Set TX/RX framebuffer count to IP default. CR-990409
 * 6.6   rsp  07/02/18 Set Vertical Flip state to IP default. CR-989453
 * </pre>
 *
 * ***************************************************************************
 */

#include "xaxivdma.h"
#include "xparameters.h"
#include "xil_exception.h"
#include "xil_printf.h"
#include "xv_tpg.h"
#include"xdsitxss.h"

//luoy add 'XV_tpg_Set_colorFormat(InstancePtr, colorFormat);' discription
//0x0 - RGB video format
//0x1 - YUV 444 video format
//0x2 - YUV 422 video format
//0x3 - YUV 420 video format

#define USE_VDMA_DEV


#ifdef XPAR_INTC_0_DEVICE_ID
#include "xintc.h"
#else
#include "xscugic.h"
#endif

#ifndef __MICROBLAZE__
#include "xpseudo_asm_gcc.h"
#endif

#if defined(XPAR_UARTNS550_0_BASEADDR)
#include "xuartns550_l.h"       /* to use uartns550 */
#endif

/******************** Constant Definitions **********************************/

/*
 * Device related constants. These need to defined as per the HW system.
 */
#define DMA_DEVICE_ID		XPAR_AXIVDMA_0_DEVICE_ID

#ifdef XPAR_INTC_0_DEVICE_ID
#define INTC_DEVICE_ID		XPAR_INTC_0_DEVICE_ID
#define VDMA_WRITE_INTR_ID		XPAR_INTC_0_AXIVDMA_0_S2MM_INTROUT_VEC_ID
#define VDMA_READ_INTR_ID		XPAR_INTC_0_AXIVDMA_0_MM2S_INTROUT_VEC_ID
#else
#define INTC_DEVICE_ID		XPAR_SCUGIC_SINGLE_DEVICE_ID
#define VDMA_WRITE_INTR_ID		XPAR_FABRIC_AXIVDMA_0_S2MM_INTROUT_VEC_ID
#define VDMA_READ_INTR_ID		XPAR_FABRIC_AXIVDMA_0_MM2S_INTROUT_VEC_ID
#endif

#ifdef XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
#define DDR_BASE_ADDR		XPAR_AXI_7SDDR_0_S_AXI_BASEADDR
#define DDR_HIGH_ADDR		XPAR_AXI_7SDDR_0_S_AXI_HIGHADDR
#elif XPAR_MIG7SERIES_0_BASEADDR
#define DDR_BASE_ADDR		XPAR_MIG7SERIES_0_BASEADDR
#define DDR_HIGH_ADDR	 	XPAR_MIG7SERIES_0_HIGHADDR
#elif XPAR_MIG_0_BASEADDR
#define DDR_BASE_ADDR		XPAR_MIG_0_BASEADDR
#define DDR_HIGH_ADDR	 	XPAR_MIG_0_HIGHADDR
#else
#warning CHECK FOR THE VALID DDR ADDRESS IN XPARAMETERS.H, \
			DEFAULT SET TO 0x01000000
//luoy this addr is ok.
//#define DDR_BASE_ADDR		0x76000000
//#define DDR_HIGH_ADDR		0x7fffffff
#define DDR_BASE_ADDR		0x10000000
#define DDR_HIGH_ADDR		0x13000000
#endif

XV_tpg   TpgInst0 ;
int g_tpg_pattern0;
#define FRM_WIDTH  1080
#define FRM_HEIGHT 2340
XDsiTxSs DsiTxSs0;
XDsi_VideoTiming g_dsi_vidtime ={0,0,0,0,0,0,0,0,0};

/* Memory space for the frame buffers
 *
 * This example only needs one set of frame buffers, because one video IP is
 * to write to the frame buffers, and the other video IP is to read from the
 * frame buffers.
 *
 * For 10 frames of 1080p, it needs 1920x1080*4*10=0x04f1a000 memory for frame buffers
 */
#define MEM_BASE_ADDR		(DDR_BASE_ADDR + 0x01000000)
#define MEM_HIGH_ADDR		DDR_HIGH_ADDR
#define MEM_SPACE		(MEM_HIGH_ADDR - MEM_BASE_ADDR)

/* Read channel and write channel start from the same place
 *
 * One video IP write to the memory region, the other video IP read from it
 */
#define READ_ADDRESS_BASE	MEM_BASE_ADDR
#define WRITE_ADDRESS_BASE	MEM_BASE_ADDR

/* Frame size related constants
 */
#define FRAME_HORIZONTAL_LEN   (FRM_WIDTH)  /* 1920 pixels, each pixel 4 bytes 0x1E00 */
#define FRAME_VERTICAL_LEN     FRM_HEIGHT   /* 1080 pixels 0x438*/

/* Subframe to be transferred by Video DMA
 *
 *|<----------------- FRAME_HORIZONTAL_LEN ---------------------->|
 * --------------------------------------------------------------------
 *|                                                                | ^
 *|                                                                | |
 *|               |<-SUBFRAME_HORIZONTAL_SIZE ->|                  | FRAME_
 *|               -----------------------------------              | VERTICAL_
 *|               |/////////////////////////////|  ^               | LEN
 *|               |/////////////////////////////|  |               | |
 *|               |/////////////////////////////|  |               | |
 *|               |/////////////////////////////| SUBFRAME_        | |
 *|               |/////////////////////////////| VERTICAL_        | |
 *|               |/////////////////////////////| SIZE             | |
 *|               |/////////////////////////////|  |               | |
 *|               |/////////////////////////////|  v               | |
 *|                ----------------------------------              | |
 *|                                                                | v
 *--------------------------------------------------------------------
 *
 * Note that SUBFRAME_HORIZONTAL_SIZE and SUBFRAME_VERTICAL_SIZE must ensure
 * to be inside the frame.
 */
#define SUBFRAME_START_OFFSET    (0)
#define SUBFRAME_HORIZONTAL_SIZE (FRAME_HORIZONTAL_LEN)
#define SUBFRAME_VERTICAL_SIZE   (FRAME_VERTICAL_LEN)

/* Number of frames to transfer
 *
 * This is used to monitor the progress of the test, test purpose only
 */
#define VDMA_INTR_FRM_NUM	10

/* Delay timer counter
 *
 * WARNING: If you are using fsync, please increase the delay counter value
 * to be 255. Because with fsync, the inter-frame delay is long. If you do not
 * care about inactivity of the hardware, set this counter to be 0, which
 * disables delay interrupt.
 */
#define DELAY_TIMER_COUNTER	16

/*
 * Device instance definitions
 */
XAxiVdma AxiVdma;

#ifdef XPAR_INTC_0_DEVICE_ID
#define INTC		XIntc
#define INTC_HANDLER	XIntc_InterruptHandler
#else
#define INTC		XScuGic
#define INTC_HANDLER	XScuGic_InterruptHandler
#endif
INTC Intc;

/* Data address
 *
 * Read and write sub-frame use the same settings
 */
static UINTPTR ReadFrameAddr;
static UINTPTR WriteFrameAddr;
static UINTPTR BlockStartOffset;
static UINTPTR BlockHoriz;
static UINTPTR BlockVert;

/* Frame-buffer count i.e Number of frames to work on
 */
static u16 ReadCount;
static u16 WriteCount;

/* DMA channel setup
 */
static XAxiVdma_DmaSetup ReadCfg;
static XAxiVdma_DmaSetup WriteCfg;

/* Transfer statics
 */
#ifdef USE_VDMA_DEV
volatile int g_VdmaIntrReadDone = 0;
volatile int g_VdmaIntrReadError = 0;
volatile int g_VdmaIntrWriteDone = 0;
volatile int g_VdmaIntrWriteError = 0;
#endif

/******************* Function Prototypes ************************************/



static int ReadSetup(XAxiVdma *InstancePtr);
static int WriteSetup(XAxiVdma * InstancePtr);
static int StartTransfer(XAxiVdma *InstancePtr);

static int SetupIntrSystem();

static void DisableIntrSystem(INTC *IntcInstancePtr);

/* Interrupt call back functions
 */
#ifdef USE_VDMA_DEV
void VdmaReadCallBack(void *CallbackRef, u32 Mask);
void VdmaReadErrorCallBack(void *CallbackRef, u32 Mask);
void VdmaWriteCallBack(void *CallbackRef, u32 Mask);
void VdmaWriteErrorCallBack(void *CallbackRef, u32 Mask);
#endif


#if defined(XPAR_UARTNS550_0_BASEADDR)
/*****************************************************************************/
/*
*
* Uart16550 setup routine, need to set baudrate to 9600 and data bits to 8
*
*
******************************************************************************/
static void Uart550_Setup(void)
{

	/* Set the baudrate to be predictable
	 */
	XUartNs550_SetBaud(XPAR_UARTNS550_0_BASEADDR,
			XPAR_XUARTNS550_CLOCK_HZ, 9600);

	XUartNs550_SetLineControlReg(XPAR_UARTNS550_0_BASEADDR,
			XUN_LCR_8_DATA_BITS);

}
#endif

/*****************************************************************************/
/**
*
* Main function
*
* This function is the main entry point of the example on DMA core. It sets up
* DMA engine to be ready to receive and send frames, and start the transfers.
* It waits for the transfer of the specified number of frame sets, and check
* for transfer errors.
*
* @return
*		- XST_SUCCESS if example finishes successfully
*		- XST_FAILURE if example fails.
*
* @note		None.
*
******************************************************************************/
int main(void)
{
	int Status;
	XAxiVdma_Config *Config;
	XAxiVdma_FrameCounter FrameCfg;

#if defined(XPAR_UARTNS550_0_BASEADDR)
	Uart550_Setup();
#endif


	ReadFrameAddr = READ_ADDRESS_BASE;
	WriteFrameAddr = WRITE_ADDRESS_BASE;
	BlockStartOffset = SUBFRAME_START_OFFSET;
	BlockHoriz = SUBFRAME_HORIZONTAL_SIZE;
	BlockVert = SUBFRAME_VERTICAL_SIZE;

	xil_printf("\r\n--- Entering main() --- \r\n");
//######## tpg dsi cfg start
    Status =XV_tpg_CfgInitialize(&TpgInst0,  XV_tpg_LookupConfig(XPAR_XV_TPG_0_DEVICE_ID),XV_tpg_LookupConfig(XPAR_XV_TPG_0_DEVICE_ID)->BaseAddress);
    if (Status != XST_SUCCESS) {
        xil_printf("TPG initial is fail \n\r") ;
        return XST_FAILURE;
      }

    Status = XDsiTxSs_CfgInitialize(&DsiTxSs0,XDsiTxSs_LookupConfig(XPAR_DSITXSS_0_DEVICE_ID),XDsiTxSs_LookupConfig(XPAR_DSITXSS_0_DEVICE_ID)->BaseAddr);
    if (Status != XST_SUCCESS) {
        xil_printf("XDSITxSs initial is fail \n\r") ;
        return XST_FAILURE;
    }

//######## tpg dsi cfg end

	/* The information of the XAxiVdma_Config comes from hardware build.
	 * The user IP should pass this information to the AXI DMA core.
	 */
	Config = XAxiVdma_LookupConfig(DMA_DEVICE_ID);
	if (!Config) {
		xil_printf("No video DMA found for ID %d\r\n", DMA_DEVICE_ID);
		return XST_FAILURE;
	}

	/* Set default read and write count based on HW config*/
	ReadCount = Config->MaxFrameStoreNum;
	WriteCount = Config->MaxFrameStoreNum;

	/* Initialize DMA engine */
	Status = XAxiVdma_CfgInitialize(&AxiVdma, Config, Config->BaseAddress);
	if (Status != XST_SUCCESS) {
		xil_printf("Configuration Initialization failed %d\r\n", Status);
		return XST_FAILURE;
	}

//######## tpg dsi cfg start
    g_tpg_pattern0 = XTPG_BKGND_COLOR_BARS;
    XV_tpg_DisableAutoRestart(&TpgInst0);
    XV_tpg_Set_width(&TpgInst0, FRM_WIDTH);
    XV_tpg_Set_height(&TpgInst0,FRM_HEIGHT);
    XV_tpg_Set_bckgndId(&TpgInst0, g_tpg_pattern0);
    XV_tpg_Set_ovrlayId(&TpgInst0, 0);
    XV_tpg_Set_motionSpeed(&TpgInst0, 2);
    XV_tpg_EnableAutoRestart(&TpgInst0);
    XV_tpg_Start(&TpgInst0);
    xil_printf("tpg ready to work  \n\r") ;

    XDsiTxSs_Activate(&DsiTxSs0, XDSITXSS_DISABLE);
    XDsiTxSs_Reset(&DsiTxSs0);
    while (!XDsiTxSs_IsControllerReady(&DsiTxSs0)) {
        xil_printf("DSI Controller NOT Ready!!!!\r\n");
    }

//33,239 is my calculating result according to BOE FAE(PengJun) timing info(Hact 1080;HBP 72;HFP 10;HSW 2).
//good panel: 33,239 is ok; additional delay 1000000us delete is OK;
//18,198 is Cris Gao's result for bad panel. According 60Hz, and vtotal, have some adjust.
    g_dsi_vidtime.HBackPorch  = 18;//44;//464;//33;//
    g_dsi_vidtime.HFrontPorch = 198;//247;//3342;//239;//
    g_dsi_vidtime.HActive     = FRM_WIDTH*3 ;

    g_dsi_vidtime.VSyncWidth  = 2;
    g_dsi_vidtime.VBackPorch  = 8;
    g_dsi_vidtime.VActive     = FRM_HEIGHT;
    g_dsi_vidtime.VFrontPorch = 8 ;

    XDsiTxSs_SetCustomVideoInterfaceTiming(&DsiTxSs0, XDSI_VM_NON_BURST_SYNC_EVENT, &g_dsi_vidtime);// XDSI_VM_NON_BURST_SYNC_EVENT//XDSI_VM_BURST_MODE

    XDsiTxSs_Activate(&DsiTxSs0, XDSITXSS_ENABLE);
    xil_printf("DSI ready to work  \n\r") ;
//######## tpg dsi cfg end


    XAxiVdma_Reset(&AxiVdma, XAXIVDMA_WRITE);
    while (XAxiVdma_ResetNotDone(&AxiVdma, XAXIVDMA_WRITE)) {
        xil_printf("VDMA reset write NOT Ready!\r\n");
    }
    XAxiVdma_Reset(&AxiVdma, XAXIVDMA_READ);
    while (XAxiVdma_ResetNotDone(&AxiVdma, XAXIVDMA_READ)) {
        xil_printf("VDMA reset read NOT Ready!\r\n");
    }

//	xdbg_printf(XDBG_DEBUG_ERROR,"xdbg_print test.\n\r");

//luoy In ip property, need set C_ENABLE_ALL=1, detail see pg020.
	Status = XAxiVdma_SetFrmStore(&AxiVdma, ReadCount,XAXIVDMA_READ);
	if (Status != XST_SUCCESS) {
		xil_printf("Setting Frame Store Number Failed in Read Channel %d\r\n", Status);
		return XST_FAILURE;
	}
	Status = XAxiVdma_SetFrmStore(&AxiVdma, WriteCount,XAXIVDMA_WRITE);
	if (Status != XST_SUCCESS) {
		xil_printf("Setting Frame Store Number Failed in Write Channel %d\r\n", Status);
		return XST_FAILURE;
	}

	/* Setup frame counter and delay counter for both channels
	 *
	 * This is to monitor the progress of the test only
	 *
	 * WARNING: In free-run mode, interrupts may overwhelm the system.
	 * In that case, it is better to disable interrupts.
	 */
	FrameCfg.ReadFrameCount = ReadCount;
	FrameCfg.WriteFrameCount = WriteCount;
	FrameCfg.ReadDelayTimerCount = DELAY_TIMER_COUNTER;
	FrameCfg.WriteDelayTimerCount = DELAY_TIMER_COUNTER;

	Status = XAxiVdma_SetFrameCounter(&AxiVdma, &FrameCfg);
	if (Status != XST_SUCCESS) {
		xil_printf("Set frame counter failed %d\r\n", Status);
		if(Status == XST_VDMA_MISMATCH_ERROR)
			xil_printf("DMA Mismatch Error\r\n");
		return XST_FAILURE;
	}

	/*
	 * Setup your video IP that writes to the memory
	 */


	/* Setup the write channel
	 */
	Status = WriteSetup(&AxiVdma);
	if (Status != XST_SUCCESS) {
		xil_printf("Write channel setup failed %d\r\n", Status);
		if(Status == XST_VDMA_MISMATCH_ERROR)
			xil_printf("DMA Mismatch Error\r\n");
		return XST_FAILURE;
	}


	/*
	 * Setup your video IP that reads from the memory
	 */

	/* Setup the read channel
	 */
	Status = ReadSetup(&AxiVdma);
	if (Status != XST_SUCCESS) {
		xil_printf("Read channel setup failed %d\r\n", Status);
		if(Status == XST_VDMA_MISMATCH_ERROR)
			xil_printf("DMA Mismatch Error\r\n");
		return XST_FAILURE;
	}

	Status = SetupIntrSystem();
	if (Status != XST_SUCCESS) {
		xil_printf("Setup interrupt system failed %d\r\n", Status);
		return XST_FAILURE;
	}

	/* Register callback functions
	 */
#ifdef USE_VDMA_DEV
	Status = XAxiVdma_SetCallBack(&AxiVdma, XAXIVDMA_HANDLER_GENERAL, VdmaReadCallBack,
	    (void *)&AxiVdma, XAXIVDMA_READ);
	if (Status != XST_SUCCESS) {
		xil_printf("Set VdmaReadCallBack failed %d\r\n", Status);
		return XST_FAILURE;
	}

	Status = XAxiVdma_SetCallBack(&AxiVdma, XAXIVDMA_HANDLER_ERROR,
	    VdmaReadErrorCallBack, (void *)&AxiVdma, XAXIVDMA_READ);
	if (Status != XST_SUCCESS) {
		xil_printf("Set VdmaReadErrorCallBack failed %d\r\n", Status);
		return XST_FAILURE;
	}

	Status = XAxiVdma_SetCallBack(&AxiVdma, XAXIVDMA_HANDLER_GENERAL,
	    VdmaWriteCallBack, (void *)&AxiVdma, XAXIVDMA_WRITE);
	if (Status != XST_SUCCESS) {
		xil_printf("Set VdmaWriteCallBack failed %d\r\n", Status);
		return XST_FAILURE;
	}

	Status = XAxiVdma_SetCallBack(&AxiVdma, XAXIVDMA_HANDLER_ERROR,
	    VdmaWriteErrorCallBack, (void *)&AxiVdma, XAXIVDMA_WRITE);
	if (Status != XST_SUCCESS) {
		xil_printf("Set VdmaWriteErrorCallBack failed %d\r\n", Status);
		return XST_FAILURE;
	}
#endif

	/* Enable your video IP interrupts if needed
	 */

#ifdef USE_VDMA_DEV
	/* Enable DMA read and write channel interrupts
	 *
	 * If interrupts overwhelms the system, please do not enable interrupt
	 */
	XAxiVdma_IntrEnable(&AxiVdma, XAXIVDMA_IXR_ALL_MASK, XAXIVDMA_WRITE);
	XAxiVdma_IntrEnable(&AxiVdma, XAXIVDMA_IXR_ALL_MASK, XAXIVDMA_READ);
#endif

	/* Start the DMA engine to transfer
	 */
	while(XAxiVdma_IsBusy(&AxiVdma, XAXIVDMA_WRITE)){
		xil_printf("WRITE XAxiVdma_IsBusy\r\n");
	}
	while(XAxiVdma_IsBusy(&AxiVdma, XAXIVDMA_READ)){
		xil_printf("READ XAxiVdma_IsBusy\r\n");
	}
	Status = StartTransfer(&AxiVdma);
	if (Status != XST_SUCCESS) {
		if(Status == XST_VDMA_MISMATCH_ERROR)
			xil_printf("DMA Mismatch Error\r\n");
		return XST_FAILURE;
	}

	/* Every set of frame buffer finish causes a completion interrupt
	 */
/*	while ((g_VdmaIntrWriteDone < VDMA_INTR_FRM_NUM) && !g_VdmaIntrReadError &&
	      (g_VdmaIntrReadDone < VDMA_INTR_FRM_NUM)) {// && !g_VdmaIntrWriteError
		;
	}

	while ((g_VdmaIntrWriteDone < VDMA_INTR_FRM_NUM) && !g_VdmaIntrWriteError &&
	      (g_VdmaIntrReadDone < VDMA_INTR_FRM_NUM)) {//&& !g_VdmaIntrReadError
		;
	}
*/
	while ((g_VdmaIntrWriteDone < VDMA_INTR_FRM_NUM) && !g_VdmaIntrReadError &&
	      (g_VdmaIntrReadDone < VDMA_INTR_FRM_NUM)) {// && !g_VdmaIntrWriteError
		;
	}

	if (g_VdmaIntrReadError || g_VdmaIntrWriteError) {//
		xil_printf("Vdma has transfer error %d/%d, Failed\r\n",g_VdmaIntrReadError, g_VdmaIntrWriteError);
		Status = XST_FAILURE;
	}
	else {
		xil_printf("Successfully ran axivdma intr Example\r\n");
	}

//	XAxiVdma_DmaStop(&AxiVdma, XAXIVDMA_READ);
//	XAxiVdma_DmaStop(&AxiVdma, XAXIVDMA_WRITE);

	xil_printf("--- Exiting main() --- \r\n");

	DisableIntrSystem(&Intc);

	if (Status != XST_SUCCESS) {
		if(Status == XST_VDMA_MISMATCH_ERROR)
			xil_printf("DMA Mismatch Error\r\n");
		return XST_FAILURE;
	}

	return XST_SUCCESS;
}


/*****************************************************************************/
/**
*
* This function sets up the read channel
*
* @param	InstancePtr is the instance pointer to the DMA engine.
*
* @return	XST_SUCCESS if the setup is successful, XST_FAILURE otherwise.
*
* @note		None.
*
******************************************************************************/
static int ReadSetup(XAxiVdma *InstancePtr)
{
	int Index;
	UINTPTR Addr;
	int Status;

	ReadCfg.VertSizeInput = SUBFRAME_VERTICAL_SIZE;
	ReadCfg.HoriSizeInput = SUBFRAME_HORIZONTAL_SIZE;

	ReadCfg.Stride = FRAME_HORIZONTAL_LEN;
	ReadCfg.FrameDelay = 0;  /* This example does not test frame delay */

	ReadCfg.EnableCircularBuf = 1;
	ReadCfg.EnableSync = 0;  /* No Gen-Lock */

	ReadCfg.PointNum = 0;    /* No Gen-Lock */
	ReadCfg.EnableFrameCounter = 0; /* Endless transfers */

	ReadCfg.FixedFrameStoreAddr = 0; /* We are not doing parking */

	Status = XAxiVdma_DmaConfig(InstancePtr, XAXIVDMA_READ, &ReadCfg);
	if (Status != XST_SUCCESS) {
		xil_printf(
		    "Read channel config failed %d\r\n", Status);

		return XST_FAILURE;
	}

	/* Initialize buffer addresses
	 *
	 * These addresses are physical addresses
	 */
	Addr = READ_ADDRESS_BASE + BlockStartOffset;
	for(Index = 0; Index < ReadCount; Index++) {
		ReadCfg.FrameStoreStartAddr[Index] = Addr;

		Addr += FRAME_HORIZONTAL_LEN * FRAME_VERTICAL_LEN;
	}

	/* Set the buffer addresses for transfer in the DMA engine
	 * The buffer addresses are physical addresses
	 */
	Status = XAxiVdma_DmaSetBufferAddr(InstancePtr, XAXIVDMA_READ,
			ReadCfg.FrameStoreStartAddr);
	if (Status != XST_SUCCESS) {
		xil_printf(
		    "Read channel set buffer address failed %d\r\n", Status);

		return XST_FAILURE;
	}

	return XST_SUCCESS;
}

/*****************************************************************************/
/**
*
* This function sets up the write channel
*
* @param	InstancePtr is the instance pointer to the DMA engine.
*
* @return	XST_SUCCESS if the setup is successful, XST_FAILURE otherwise.
*
* @note		None.
*
******************************************************************************/
static int WriteSetup(XAxiVdma * InstancePtr)
{
	int Index;
	UINTPTR Addr;
	int Status;

	WriteCfg.VertSizeInput = SUBFRAME_VERTICAL_SIZE;
	WriteCfg.HoriSizeInput = SUBFRAME_HORIZONTAL_SIZE;

	WriteCfg.Stride = FRAME_HORIZONTAL_LEN;
	WriteCfg.FrameDelay = 0;  /* This example does not test frame delay */

	WriteCfg.EnableCircularBuf = 1;
	WriteCfg.EnableSync = 0;  /* No Gen-Lock */

	WriteCfg.PointNum = 0;    /* No Gen-Lock */
	WriteCfg.EnableFrameCounter = 0; /* Endless transfers */

	WriteCfg.FixedFrameStoreAddr = 0; /* We are not doing parking */

	WriteCfg.EnableVFlip = 1; /* Enable vertical flip */

	Status = XAxiVdma_DmaConfig(InstancePtr, XAXIVDMA_WRITE, &WriteCfg);
	if (Status != XST_SUCCESS) {
		xil_printf(
		    "Write channel config failed %d\r\n", Status);

		return XST_FAILURE;
	}

	/* Initialize buffer addresses
	 *
	 * Use physical addresses
	 */
	Addr = WRITE_ADDRESS_BASE + BlockStartOffset;
	for(Index = 0; Index < WriteCount; Index++) {
		WriteCfg.FrameStoreStartAddr[Index] = Addr;

		Addr += FRAME_HORIZONTAL_LEN * FRAME_VERTICAL_LEN;
	}

	/* Set the buffer addresses for transfer in the DMA engine
	 */
	Status = XAxiVdma_DmaSetBufferAddr(InstancePtr, XAXIVDMA_WRITE,
	        WriteCfg.FrameStoreStartAddr);
	if (Status != XST_SUCCESS) {
		xil_printf(
		    "Write channel set buffer address failed %d\r\n", Status);

		return XST_FAILURE;
	}

	/* Clear data buffer
	 */
	memset((void *)WriteFrameAddr, 0,
	    FRAME_HORIZONTAL_LEN * FRAME_VERTICAL_LEN * WriteCount);

	return XST_SUCCESS;
}

/*****************************************************************************/
/**
*
* This function starts the DMA transfers. Since the DMA engine is operating
* in circular buffer mode, video frames will be transferred continuously.
*
* @param	InstancePtr points to the DMA engine instance
*
* @return	XST_SUCCESS if both read and write start succesfully
*		XST_FAILURE if one or both directions cannot be started
*
* @note		None.
*
******************************************************************************/
static int StartTransfer(XAxiVdma *InstancePtr)
{
	int Status;

	Status = XAxiVdma_DmaStart(InstancePtr, XAXIVDMA_WRITE);
	if (Status != XST_SUCCESS) {
		xil_printf(
		    "Start Write transfer failed %d\r\n", Status);

		return XST_FAILURE;
	}

	Status = XAxiVdma_DmaStart(InstancePtr, XAXIVDMA_READ);
	if (Status != XST_SUCCESS) {
		xil_printf(
		    "Start read transfer failed %d\r\n", Status);

		return XST_FAILURE;
	}

	return XST_SUCCESS;
}

/*****************************************************************************/
/*
*
* This function setups the interrupt system so interrupts can occur for the
* DMA.  This function assumes INTC component exists in the hardware system.
*
* @param	AxiDmaPtr is a pointer to the instance of the DMA engine
*
* @return	XST_SUCCESS if successful, otherwise XST_FAILURE.
*
* @note		None.
*
******************************************************************************/
static int SetupIntrSystem()
{
	int Status;

#ifdef XPAR_INTC_0_DEVICE_ID
	XIntc *IntcInstancePtr =&Intc;


	/* Initialize the interrupt controller and connect the ISRs */
	Status = XIntc_Initialize(IntcInstancePtr, INTC_DEVICE_ID);
	if (Status != XST_SUCCESS) {

		xil_printf( "Failed init intc\r\n");
		return XST_FAILURE;
	}
    #ifdef USE_VDMA_DEV
	Status = XIntc_Connect(IntcInstancePtr, VDMA_READ_INTR_ID,
	         (XInterruptHandler)XAxiVdma_ReadIntrHandler, &AxiVdma);
	if (Status != XST_SUCCESS) {

		xil_printf(
		    "Failed read channel connect intc %d\r\n", Status);
		return XST_FAILURE;
	}

	Status = XIntc_Connect(IntcInstancePtr, VDMA_WRITE_INTR_ID,
	         (XInterruptHandler)XAxiVdma_WriteIntrHandler, &AxiVdma);
	if (Status != XST_SUCCESS) {

		xil_printf(
		    "Failed write channel connect intc %d\r\n", Status);
		return XST_FAILURE;
	}
    #endif

	/* Start the interrupt controller */
	Status = XIntc_Start(IntcInstancePtr, XIN_REAL_MODE);
	if (Status != XST_SUCCESS) {

		xil_printf( "Failed to start intc\r\n");
		return XST_FAILURE;
	}

	/* Enable interrupts from the hardware */
    #ifdef USE_VDMA_DEV
	XIntc_Enable(IntcInstancePtr, VDMA_READ_INTR_ID);
	XIntc_Enable(IntcInstancePtr, VDMA_WRITE_INTR_ID);
    #endif

	Xil_ExceptionInit();
	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
			(Xil_ExceptionHandler)INTC_HANDLER,
			(void *)IntcInstancePtr);

	Xil_ExceptionEnable();

#else //for ZYNQ_CPU

	XScuGic *IntcInstancePtr = &Intc;	/* Instance of the Interrupt Controller */
	XScuGic_Config *IntcConfig;


	/*
	 * Initialize the interrupt controller driver so that it is ready to
	 * use.
	 */
	IntcConfig = XScuGic_LookupConfig(INTC_DEVICE_ID);
	if (NULL == IntcConfig) {
		return XST_FAILURE;
	}

	Status = XScuGic_CfgInitialize(IntcInstancePtr, IntcConfig,
					IntcConfig->CpuBaseAddress);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}

    #ifdef USE_VDMA_DEV
	XScuGic_SetPriorityTriggerType(IntcInstancePtr, VDMA_READ_INTR_ID, 0xA0, 0x3);
	XScuGic_SetPriorityTriggerType(IntcInstancePtr, VDMA_WRITE_INTR_ID, 0xA0, 0x3);
    #endif

    #ifdef USE_VDMA_DEV
	Status = XScuGic_Connect(IntcInstancePtr, VDMA_READ_INTR_ID,
				(Xil_InterruptHandler)XAxiVdma_ReadIntrHandler,
				&AxiVdma);
	if (Status != XST_SUCCESS) {
		return Status;
	}

	Status = XScuGic_Connect(IntcInstancePtr, VDMA_WRITE_INTR_ID,
				(Xil_InterruptHandler)XAxiVdma_WriteIntrHandler,
				&AxiVdma);
	if (Status != XST_SUCCESS) {
		return Status;
	}
    #endif

    #ifdef USE_VDMA_DEV
	XScuGic_Enable(IntcInstancePtr, VDMA_READ_INTR_ID);
	XScuGic_Enable(IntcInstancePtr, VDMA_WRITE_INTR_ID);
    #endif

	Xil_ExceptionInit();

	/*
	 * Connect the interrupt controller interrupt handler to the hardware
	 * interrupt handling logic in the processor.
	 */
	Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT,
				(Xil_ExceptionHandler)INTC_HANDLER,
				IntcInstancePtr);


	/*
	 * Enable interrupts in the Processor.
	 */
	Xil_ExceptionEnable();


#endif

	return XST_SUCCESS;
}

/*****************************************************************************/
/**
*
* This function disables the interrupts
*
*
* @return	None.
*
* @note		None.
*
******************************************************************************/
static void DisableIntrSystem(INTC *IntcInstancePtr)
{

#ifdef XPAR_INTC_0_DEVICE_ID
    #ifdef USE_VDMA_DEV
	XIntc_Disconnect(IntcInstancePtr, VDMA_READ_INTR_ID);
	XIntc_Disconnect(IntcInstancePtr, VDMA_WRITE_INTR_ID);
    #endif
#else //for ZYNQ_CPU

    #ifdef USE_VDMA_DEV
	XScuGic_Disable(IntcInstancePtr, VDMA_READ_INTR_ID);
	XScuGic_Disable(IntcInstancePtr, VDMA_WRITE_INTR_ID);
    #endif

    #ifdef USE_VDMA_DEV
	XScuGic_Disconnect(IntcInstancePtr, VDMA_READ_INTR_ID);
	XScuGic_Disconnect(IntcInstancePtr, VDMA_WRITE_INTR_ID);
    #endif
#endif
}

#ifdef USE_VDMA_DEV
void VdmaReadCallBack(void *CallbackRef, u32 Mask)
{

	if (Mask & XAXIVDMA_IXR_FRMCNT_MASK) {
		g_VdmaIntrReadDone += 1;
	}
}

void VdmaReadErrorCallBack(void *CallbackRef, u32 Mask)
{

	if (Mask & XAXIVDMA_IXR_ERROR_MASK) {
		g_VdmaIntrReadError += 1;
	}
}

void VdmaWriteCallBack(void *CallbackRef, u32 Mask)
{

	if (Mask & XAXIVDMA_IXR_FRMCNT_MASK) {
		g_VdmaIntrWriteDone += 1;
	}
}

void VdmaWriteErrorCallBack(void *CallbackRef, u32 Mask)
{

	if (Mask & XAXIVDMA_IXR_ERROR_MASK) {
		g_VdmaIntrWriteError += 1;
	}
}
#endif

 

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Re: [Video Series 26] - Question about the memory use

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Hi @luoyanghero 

The DEBUG_MODE was probably from an old example and not available anymore


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Re: [Video Series 26] - Question about the memory use

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@florentw I changed some property for bebug(CONFIG.c_enable_all=1) and interrupt(CONFIG.c_enable_mm2s_frmstr_reg=1), default setting c_enable_mm2s_frmstr_reg=0, but interrupt need c_enable_mm2s_frmstr_reg=1, why?

The config picture is in my last post. I edited it just now.

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Re: [Video Series 26] - Question about the memory use

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@florentw 

I use mipi-dsi-tx to show my VDMA read result. Visually it is my expect. But it still has some strange things(like write interrupt error, Bytes number must be 8 times, not 4 times). So I want to check My VDMA read-write design data-by-data.

How Can I diff the VDMA IP read-write data is same?

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Re: [Video Series 26] - Question about the memory use

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@luoyanghero wrote:

@florentw 

I use mipi-dsi-tx to show my VDMA read result. Visually it is my expect. But it still has some strange things(like write interrupt error, Bytes number must be 8 times, not 4 times). So I want to check My VDMA read-write design data-by-data.

How Can I diff the VDMA IP read-write data is same?


> Write a pattern you know and just check it... You need to write your own logic for this. There is no magic block


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Registered: ‎11-24-2016

Re: [Video Series 26] - Question about the memory use

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@florentw 

I use vivado 2018.3 'axivdma_v6_6' example driver code to config my vdma IP.

1. In the driver code, it needs frame_width, sub_frame_width, offset must be multiple of axifull_width_byte. I follow to this limiting, all strange phenomenon disappeared.

2. If I use your example  config, the above limiting I will not find, and will cause some bug.

3. If unaligned setting be effective, must axi_width_bit >=64bit.

 

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Re: [Video Series 26] - Question about the memory use

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HI @luoyanghero 

Again, this is mentioned on the note of my video series that the offset should be a multiple axifull_width_byte. My code is not checking if the value is correct as I am using direct registers programing


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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View solution in original post

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Re: [Video Series 26] - Question about the memory use

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I did not read your note triple-times^_^.
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Re: [Video Series 26] - Question about the memory use

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Hi @luoyanghero 

Is everything clear for you on this subject? If yes could you kindly close the topic by marking your previous observations as accepted solution to close the thread?

Thanks


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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