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Video frame looks orders were changed (NTSC with 2VDMA)

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Visitor
Posts: 7
Registered: ‎10-05-2017

Video frame looks orders were changed (NTSC with 2VDMA)

Hello guys,

 

I designed NTSC(RS170) video output (1280 X 480 resolution and 30Hz frame rates, pclk 24.54MHz with 2 VDMA

but the result is poor when I moved the camera, it sometimes(frequently) looks video frame orders are changed(video looks vibrated) but sometimes ok.

 

in my design,(VIVADO 16.3)

1. input image(1280 X 480, mono 16bit, 40MHz, 30Hz)

2. vid2axi4s : changed to axis

3. vdma1 : to change pclk from 40M to 49.08MHz

- frame buffer : 3

- write channel option : fsync(s2mm tuser), genlock(Dynamic Master), allow unaligned transfers checked

- read channel option : fsync(none), genlock(Dynamic Slave), allow unaligned transfers checked

4-1. vdma 2 : to output interlaced video, with 24.54MHz

- frame buffer : 4

- write channel option : fsync(s2mm tuser), genlock(Dynamic Slave)

- read channel option : fsync(none), genlock(Dynamic Master)

4-2. VTC : timing generator

5. axi4s2vidout : NTSC output

 

SDK VDMA REGISTER SET

FrameDelay = 0;

EnableCircularBuf = 1;

EnableSync = 1;

PointNum  = 0;

EnableFrameCounter = 0;

FixedFrameStoreAddr = 0;

 

 

I tried to resolve this issue like below but I couldn't get the good result

1. change set the both or one of vdma set(dynamic genlock to genlock)

2. change set the VDMA2 channel option

 - Read(Dynamic Slave), Write(Dynamic Master)

3. increasing frame buffer (VDMA1 : 3 to 6,  VDMA2 : 4 to 8)

4. all vdma allow unaligned transfers checked

5. all vdma allow unaligned transfers unchecked

Moderator
Posts: 48
Registered: ‎10-04-2017

Re: Video frame looks orders were changed (NTSC with 2VDMA)

Hi @jinhanharu,

 

My first thought is that something is wrong with how you are using genlock with the interlaced VDMA core, but I need some more information.

 

Can you provide a screenshot of your block design?

Can you provide a screenshot of the VDMA core that is doing the interlacing?

What are you setting the vsize, hsize, and stride register values to?

 

Also is there any backpressure in your system?  (ready signals going low)

Do any of your cores report any overflow?

 

Regards,

Sam

 

Don't forget to reply, kudo, and accept as solution.

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