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Anonymous
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Video phy controller simulation

Hello,

 

I am using Vivado 2016.2 version.

I configured Video phy controller for HDMI rx only.

Then, I tried to simulate Video phy controller but It doesn't have any IP example design.

 

So, I created a simple tb to provide "mgtrefclk0_pad_p(n)_in, video_phy_sb_ack, video_phy_axi4lite_aclk" like xapp1275.

But Video phy doesn't work. No rxoutclk and No reset done signal.

 

From PG230, I also tried software reset after writing RX reset register (0x0024).

But still I couldn't see reset done signal.

 

How should I set up Video phy to generate rxoutclk at least?

 

Sincerely,

 

Is there any reference how to configure 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-01-2008

Re: Video phy controller simulation

the xapp tested on Vivado 2015.4 . Please use supported version

Here is some known issue my xapp
https://forums.xilinx.com/t5/DSP-and-Video/XAPP1275-HDMI-RX-TX-design-of-s-axis-video-aclk/td-p/698513
Thanks and Regards
Balkrishan
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Anonymous
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Re: Video phy controller simulation

Thank you for reply.

 

But In my case, I only considered HDMI RX.

So vid_phy_rx_axi4s_aclk is connected to rxoutclk like xapp1275 and rx_video_clk should be generated from Video Phy.

 

Here, I didn't consider the xapp1275 application but rather I only tried to simulate Video Phy IP core.

Video Phy IP core should work at Vivado 2016.2 

Also, Both Vivado version include the same  Video phy version (2.0).

 

Sincerely,

 

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