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Scholar
Scholar
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Registered: ‎11-09-2013

ZCU102, Zynq MPSoC DisplayPort clocking

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trying again with more specific problem, ZCU102 TRD uses si570 as DP clock in devicetree, this clock is not used in hardware but it can not be removed from devicetree, so what is the solution?

 

if we wand the si570 to be use for other clock then DP, how should we then decribe Xilinx DP DRM in devicetree?

 

DP itself works, both in 1 lane and 2 lane configurations, pretty cool

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Scholar
Scholar
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Registered: ‎11-09-2013

Re: ZCU102, Zynq MPSoC DisplayPort clocking

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problem identified workaround implemented.

 

waiting for the FIX, 2016.3 ? or 2016.4 well need wait and hope..

View solution in original post

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Scholar
Scholar
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Registered: ‎11-09-2013

Re: ZCU102, Zynq MPSoC DisplayPort clocking

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Partially solved, we have succesfully removed si570 entry from devicetree and still have picture on DisplayPort monitor

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Highlighted
Scholar
Scholar
9,460 Views
Registered: ‎11-09-2013

Re: ZCU102, Zynq MPSoC DisplayPort clocking

Jump to solution

problem identified workaround implemented.

 

waiting for the FIX, 2016.3 ? or 2016.4 well need wait and hope..

View solution in original post

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