UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
215 Views
Registered: ‎06-20-2018

ZCU102 vid_phy_controller

Jump to solution
 
Tags (2)
0 Kudos
1 Solution

Accepted Solutions
Moderator
Moderator
140 Views
Registered: ‎10-04-2017

Re: ZCU102 vid_phy_controller

Jump to solution

Hi @chrischan,


The SI5324 is used on the ZCU102/ZCU104/ZCU106 boards to provide the TX GTREFCLK. If you are doing a passthrough design and want to use the received RX clock, this is passed to the SI5324 from the RX side of the Video PHY controller.

 

Take a look at Figure 5-4 on page 65 of PG235.

 

2019-06-17 15_04_25-Xilinx Documentation Navigator 2018.3 -  https___www.xilinx.com_support_document.png

 

 

 

This follows our clocking recommendation shown in figure 9 of PG230

2019-06-17 15_09_25-Xilinx Documentation Navigator 2018.3 -  https___www.xilinx.com_support_document.png

 

** As a note, I believe the clock rate from the SI5324 is controlled over IIC by the software drivers.

Take a look at the bare metal example designs provided for HDMI. These are listed in chapter 5 of the PG.

 

 

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
3 Replies
Contributor
Contributor
212 Views
Registered: ‎06-20-2018

Re: ZCU102 vid_phy_controller

Jump to solution

I am trying to understanding how HDMI TX subsystem work in ZCU102 TRD,  There is a vid_phy_contoller in BD and I trace the MGTREFCLK0_P/N_IN ( HDMI_SI5324_OUT_C_P/N ) on ZCU102 schematic, there are driven by si5324 as the signal name implemented, the CKIN1_P/N pin  on si5324 is driven by FPGA, I look into the wrapper file and they are not being defined. Basically, CKIN1_P/N on si5324 is floating, so the only way it will work is Si5324 was set up to Free Run Mode, can you confirm?

 

Thanks

Chris

Tags (2)
0 Kudos
Moderator
Moderator
141 Views
Registered: ‎10-04-2017

Re: ZCU102 vid_phy_controller

Jump to solution

Hi @chrischan,


The SI5324 is used on the ZCU102/ZCU104/ZCU106 boards to provide the TX GTREFCLK. If you are doing a passthrough design and want to use the received RX clock, this is passed to the SI5324 from the RX side of the Video PHY controller.

 

Take a look at Figure 5-4 on page 65 of PG235.

 

2019-06-17 15_04_25-Xilinx Documentation Navigator 2018.3 -  https___www.xilinx.com_support_document.png

 

 

 

This follows our clocking recommendation shown in figure 9 of PG230

2019-06-17 15_09_25-Xilinx Documentation Navigator 2018.3 -  https___www.xilinx.com_support_document.png

 

** As a note, I believe the clock rate from the SI5324 is controlled over IIC by the software drivers.

Take a look at the bare metal example designs provided for HDMI. These are listed in chapter 5 of the PG.

 

 

 

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
Moderator
Moderator
82 Views
Registered: ‎11-09-2015

Re: ZCU102 vid_phy_controller

Jump to solution

Hi @samk 

Do you have any update? Was @samk 's reply enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos