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Contributor
Contributor
2,464 Views
Registered: ‎06-10-2018

ZYNQ Video Mixer design

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I'm trying to implement a basic video mixer design on a ZYNQ 7020 device without any memeory layer,  all are streaming layers.

Removing the video mixer and using a single TPG works fine. When using the video mixer nothing shows up on screen. Can anyone see anything wrong with the design?

 

Untitled.png

 

I'm using the following code to initialize the mixer. Before it I initialize the VTC, and TPG, 0,1,2.

    XV_mix 				xv_mix;
    XV_mix_Config 		*xv_config;

    xv_config = XV_mix_LookupConfig(XPAR_XV_MIX_0_DEVICE_ID);
    XV_mix_CfgInitialize(&xv_mix,xv_config,xv_config->BaseAddress);


    XV_mix_Set_HwReg_width(&xv_mix, (u32)1920);
    XV_mix_Set_HwReg_height(&xv_mix, (u32) 1800);
 	XV_mix_Set_HwReg_layerEnable(&xv_mix,(u32)3);


 	XV_mix_Set_HwReg_layerStartX_0(&xv_mix,(u32)0);
 	XV_mix_Set_HwReg_layerStartY_0(&xv_mix,0);
 	XV_mix_Set_HwReg_layerWidth_0(&xv_mix,(u32)640);
 	XV_mix_Set_HwReg_layerHeight_0(&xv_mix,(u32)400);
 	//XV_mix_Set_HwReg_layerAlpha_0(&xv_mix, 255);

 	XV_mix_Set_HwReg_layerStartX_1(&xv_mix,640);
 	XV_mix_Set_HwReg_layerStartY_1(&xv_mix,400);
 	XV_mix_Set_HwReg_layerWidth_1(&xv_mix,(u32)640);
 	XV_mix_Set_HwReg_layerHeight_1(&xv_mix,(u32)400);
 	//XV_mix_Set_HwReg_layerAlpha_1(&xv_mix, 255);

	xil_printf("/* Mixer configured               */\n\r");

 	XV_mix_EnableAutoRestart(&xv_mix);
 	XV_mix_Start(&xv_mix);

	xil_printf("/* Mixer started               */\n\r");

 

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Contributor
Contributor
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Registered: ‎06-10-2018

Re: ZYNQ Video Mixer design

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Hi @samk,

 

Just to confirm, the information above is incorrect. The master layer should match the resolution of the frame , the rest of the layers can have different resolutions.

Althoutgh it's flakey sometimes it works for 1 sec and then the video feed abruptly cuts off.

 

The following issues were parts of the resolution:

a) enable all the sources prior to enabling the mixer (meantioned in the PG)

b) use an external GPIO reset ( not meantioned)

c) check correctness of window settings for each stream.

 

 

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27 Replies
Moderator
Moderator
2,399 Views
Registered: ‎10-04-2017

Re: ZYNQ Video Mixer design

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Hi @dimiter,

 

Can you check the registers to make sure that you are setting the values correctly?

If all of the registers are being set as you expect, put an ILA in the system to check for backpressure and that the stream sizes are being set correctly.

 

If the registers are being set to the wrong size, there will likely be an issue as well as underflow/overflow backpressure.

Don't forget to reply, kudo, and accept as solution.

Xilinx Video Design Hub
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Xilinx Employee
Xilinx Employee
2,390 Views
Registered: ‎03-04-2018

Re: ZYNQ Video Mixer design

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Hello @dimiter ,

 

As samk mentioned, please check your value and sequence?  Also I recommend the PG243 as a reference.  It shows an example design and SDK.  I hope it would be helpful for understanding.

https://www.xilinx.com/support/documentation/ip_documentation/v_mix/v4_0/pg243-v-mix.pdf

 

Best regards,

kshimizu 

Product Application Engineer Xilinx Technical Support

-------------------------------------------------------

Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.  Please Give Kudos.

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Contributor
Contributor
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Registered: ‎06-10-2018

Re: ZYNQ Video Mixer design

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Hello @kshimizu, @samk ,

I already went over the PG243  app note.

It would have been nice if there was a ZC702 or generic ZYNQ based reference to use as a baseline.

The reference design does not use ZYNQ or Ultrascale but Microblaze.

 

Anyways, after I start the mixer core i ended up using the debug calls from the API.

I still get a blank screen. I instrumented the design with 3 ILA and I see none of them outputs data which implies somehow the mixer is throtling them since the TPG works fine without it.

 

XV_mix_EnableAutoRestart(&xv_mix);
XV_mix_Start(&xv_mix);


XVMix_DbgReportStatus(&xv_mixl2);

XVMix_DbgLayerInfo(&xv_mixl2,0);
XVMix_DbgLayerInfo(&xv_mixl2,1);
XVMix_DbgLayerInfo(&xv_mixl2,2);

 

TPG 1 started!
TPG 1 started!
TPG 2 started!


----->MIXER STATUS<----
Pixels Per Clock: 1
Color Depth:      8
Number of Layers: 3
Control Reg:      0x84
Layer Enable Reg: 0x1

Layer Master: Enabled
Layer 1     : Disabled
Layer 2     : Disabled
Layer 3     : Disabled
Layer 4     : Disabled
Layer 5     : Disabled
Layer 6     : Disabled
Layer 7     : Disabled
Layer 8     : Disabled
Layer 9     : Disabled
Layer 10     : Disabled
Layer 11     : Disabled
Layer 12     : Disabled
Layer 13     : Disabled
Layer 14     : Disabled
Layer Logo  : Disabled

Background Color Y/R: 0
Background Color U/G: 0
Background Color V/B: 255

/* Mixer configured               */



----->MIXER STATUS<----
Pixels Per Clock: 1
Color Depth:      8
Number of Layers: 3
Control Reg:      0x81
Layer Enable Reg: 0x7

Layer Master: Enabled
Layer 1     : Enabled
Layer 2     : Enabled
Layer 3     : Disabled
Layer 4     : Disabled
Layer 5     : Disabled
Layer 6     : Disabled
Layer 7     : Disabled
Layer 8     : Disabled
Layer 9     : Disabled
Layer 10     : Disabled
Layer 11     : Disabled
Layer 12     : Disabled
Layer 13     : Disabled
Layer 14     : Disabled
Layer Logo  : Disabled

Background Color Y/R: 0
Background Color U/G: 0
Background Color V/B: 255



----->Master Layer Status<----
State: Enabled
Color Format: RGB

Resolution: 1920 x 1800
Stream Info->
	Color Format:     RGB
	Color Depth:      8
	Pixels Per Clock: 1
	Mode:             Progressive
	Frame Rate:       60Hz
	Resolution:       1920x1080 [Custom Mode]
	Pixel Clock:      0


----->Layer 1 Status<----
State: Enabled
Type : Stream
Addr : 0x0
Chroma Addr : 0x0
Alpha: Disabled
Scale: Disabled
Color Format: RGB

Window Data: 
   Start X    = 640
   Start Y    = 400
   Win Width  = 640
   Win Height = 400
   Win Stride = 0


----->Layer 2 Status<----
State: Enabled
Type : Stream
Addr : 0x0
Chroma Addr : 0x0
Alpha: Disabled
Scale: Disabled
Color Format: RGB

Window Data: 
   Start X    = 0
   Start Y    = 0
   Win Width  = 0
   Win Height = 0
   Win Stride = 0
/* Mixer started               */

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Contributor
Contributor
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Registered: ‎06-10-2018

Re: ZYNQ Video Mixer design

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I ported the design to a ZC702 board using some of the material by @florentw  on the AXIS video series.

The problem is the when configuring the mixer the master layer pixel clock is 0.

This is sourced from FCLK_CLK0 which is 150Mhz, while the VTC clk and Video out AXIS clock are sourced from a 40Mhz clock for an 800x600 resolution.

i don't understand why is the mixer core reporting that the master stream pixel clock is 0.

 

HDMI IIC configured

HDMI Monitor connected
HDMI Setup Complete!
TPG1 setup!
TPG started!
TPG2 setup!
TPG started!
TPG2 setup!
TPG started!
 Setup VTC and display mode Complete!
/* Mixer Configuration               */



----->MIXER STATUS<----
Pixels Per Clock: 1
Color Depth:      8
Number of Layers: 3
Control Reg:      0x81
Layer Enable Reg: 0x1

Layer Master: Enabled
Layer 1     : Disabled
Layer 2     : Disabled
Layer 3     : Disabled
Layer 4     : Disabled
Layer 5     : Disabled
Layer 6     : Disabled
Layer 7     : Disabled
Layer 8     : Disabled
Layer 9     : Disabled
Layer 10     : Disabled
Layer 11     : Disabled
Layer 12     : Disabled
Layer 13     : Disabled
Layer 14     : Disabled
Layer Logo  : Disabled

Background Color Y/R: 0
Background Color U/G: 0
Background Color V/B: 255

/* Mixer configured               */



----->MIXER STATUS<----
Pixels Per Clock: 1
Color Depth:      8
Number of Layers: 3
Control Reg:      0x81
Layer Enable Reg: 0x7

Layer Master: Enabled
Layer 1     : Enabled
Layer 2     : Enabled
Layer 3     : Disabled
Layer 4     : Disabled
Layer 5     : Disabled
Layer 6     : Disabled
Layer 7     : Disabled
Layer 8     : Disabled
Layer 9     : Disabled
Layer 10     : Disabled
Layer 11     : Disabled
Layer 12     : Disabled
Layer 13     : Disabled
Layer 14     : Disabled
Layer Logo  : Disabled

Background Color Y/R: 0
Background Color U/G: 0
Background Color V/B: 255



----->Master Layer Status<----
State: Enabled
Color Format: YUV_422

Resolution: 800 x 600
Stream Info->
	Color Format:     YUV_422
	Color Depth:      8
	Pixels Per Clock: 1
	Mode:             Progressive
	Frame Rate:       60Hz
	Resolution:       800x600 [Custom Mode]
	Pixel Clock:      0


----->Layer 1 Status<----
State: Enabled
Type : Stream
Addr : 0x0
Chroma Addr : 0x0
Alpha: 255
Scale: 1x
Color Format: YUV_422

Window Data: 
   Start X    = 400
   Start Y    = 0
   Win Width  = 400
   Win Height = 300
   Win Stride = 0


----->Layer 2 Status<----
State: Enabled
Type : Stream
Addr : 0x0
Chroma Addr : 0x0
Alpha: 255
Scale: 1x
Color Format: YUV_422

Window Data: 
   Start X    = 0
   Start Y    = 0
   Win Width  = 400
   Win Height = 300
   Win Stride = 0
/* Mixer started               */
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Contributor
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Registered: ‎06-10-2018

Re: ZYNQ Video Mixer design

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Hello @kshimizu  and @samk 

Can you explain what do you mean by sequence? What I am trying to do is tile 4 TPG's side by side.

I cannot find any example with streaming layers so I have the following questions:

a) Is it a must to use an AXI GPIO to reset the unit before configuration.

b)

What I notice is that if I try to uncomment XVMix_MoveLayerWindow() for the master window the program freezes Deos the mixer support showing only a part of a 800x600 TPG if you want to tile two images side by side or should the stream already be prescaled one it piped to the mixer?

 

I have instrumented the design with two ILA's before and after the mixer and I see there is data on the AXIS bus both before and after the mixer.

The clock is also configured correctly for an by 800x600 resolution according to the debug output. I tried setting the width of the TPG to 400x300 so they can fit inside the area but there is no pattern on the display.

 

mixersettings.pngsuibset.pngtop.png

 

 

#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"

#include "iic_utils.h"
#include "xv_tpg.h"
#include "zc702_hw.h"
#include "xvidc.h"
#include "xgpio.h"

#include "xv_mix.h"
#include "xv_mix_l2.h"
#include "vga_modes.h"

#include "xvtc.h"


#define H_STRIDE            800
#define H_ACTIVE            800
#define V_ACTIVE            600

#define VIDEO_LENGTH  (H_STRIDE*V_ACTIVE)


/* ------------------------------------------------------------ */
/*				Procedure Definitions							*/
/* ------------------------------------------------------------ */

XIicPs 				IicPs_inst;
XV_tpg 				tpg_inst, tpg_inst1, tpg_inst2, tpg_inst3;
XV_tpg_Config 		*tpg_config, *tpg_config1, *tpg_config2, *tpg_config3;
XV_mix 				xv_mix;
XV_mix_Config 		*xv_config;
XV_Mix_l2 			xv_mixl2;

XVtc 				vtc; /*VTC driver struct*/
XVtc_Config 		*vtcConfig;
XVtc_Timing 		XVtc_Timingconf;

XGpio gpio0;

void showFusion(void);

int main()
{
	int Status;
    init_platform();

	Status = XGpio_Initialize(&gpio0, XPAR_AXI_GPIO_0_DEVICE_ID);
	if (Status != XST_SUCCESS) {
		xil_printf("Gpio 1 Initialization Failed\r\n");
		return XST_FAILURE;
	}
	/* Set the direction for all signals as inputs except the LED output */
	XGpio_SetDataDirection(&gpio0, 1, 0);	// Set as output 0x00



    print("Mixer application on ZC702 using on-board HDMI\n\r");

    //Configure the PS IIC Controller
    ps_iic_init(XPAR_XIICPS_0_DEVICE_ID, &IicPs_inst);

    // Set the iic mux to the ADV7511
    set_iic_mux(&IicPs_inst, ZC702_I2C_SELECT_HDMI, ZC702_I2C_MUX_ADDR);
    print("1. HDMI IIC configured\n\r");
    //Wait for the monitor to be connected
    wait_for_monitor(&IicPs_inst, ZC702_HDMI_ADDR);

    // ADV7511 Basic Configuration
    configure_adv7511(&IicPs_inst,ZC702_HDMI_ADDR);
    // ADV7511 ZC702 Specific configuration
    configure_adv7511_zc702(&IicPs_inst,ZC702_HDMI_ADDR);

    xil_printf("2. HDMI Setup Complete!\r\n");
    xil_printf("3. TPG units setup!\r\n");

    /*************************************************************************************/
    /* Insert the code for the TPG here */
    Status = XV_tpg_Initialize(&tpg_inst, XPAR_V_TPG_0_DEVICE_ID);
    if(Status!= XST_SUCCESS)
    {
    	xil_printf("TPG configuration failed\r\n");
        	return(XST_FAILURE);
    }
    // Set Resolution to 800x600
    XV_tpg_Set_height(&tpg_inst, 600);
    XV_tpg_Set_width(&tpg_inst, 800);
    // Set Color Space to YUV422
    XV_tpg_Set_colorFormat(&tpg_inst, XVIDC_CSF_YCRCB_422);
    //Start the TPG
    XV_tpg_EnableAutoRestart(&tpg_inst);
    XV_tpg_Start(&tpg_inst);
    // Change the pattern to color bar
    XV_tpg_Set_bckgndId(&tpg_inst, XTPG_BKGND_COLOR_BARS);
    //Start the TPG
    // Set Overlay to moving box
    // Set the size of the box
    XV_tpg_Set_boxSize(&tpg_inst, 50);
    // Set the speed of the box
    XV_tpg_Set_motionSpeed(&tpg_inst, 5);
    XV_tpg_Set_boxColorR(&tpg_inst,138);
    XV_tpg_Set_boxColorG(&tpg_inst,222);
    XV_tpg_Set_boxColorB(&tpg_inst,79);
    // Enable the moving box
    XV_tpg_Set_ovrlayId(&tpg_inst, 1);
    xil_printf("4. TPG 0 started!\r\n");


    Status = XV_tpg_Initialize(&tpg_inst1, XPAR_V_TPG_1_DEVICE_ID);
    if(Status!= XST_SUCCESS)
    {
    	xil_printf("TPG configuration failed\r\n");
        	return(XST_FAILURE);
    }
    XV_tpg_Set_height(&tpg_inst1, 600);
    XV_tpg_Set_width(&tpg_inst1, 800);
    XV_tpg_Set_colorFormat(&tpg_inst1, XVIDC_CSF_YCRCB_422);
    XV_tpg_Set_bckgndId(&tpg_inst1, XTPG_BKGND_TARTAN_COLOR_BARS);
    XV_tpg_EnableAutoRestart(&tpg_inst1);
    XV_tpg_Start(&tpg_inst1);


    Status = XV_tpg_Initialize(&tpg_inst2, XPAR_V_TPG_2_DEVICE_ID);
     if(Status!= XST_SUCCESS)
     {
     	xil_printf("TPG configuration failed\r\n");
         	return(XST_FAILURE);
     }
     XV_tpg_Set_height(&tpg_inst2, 600);
     XV_tpg_Set_width(&tpg_inst2, 800);
     XV_tpg_Set_colorFormat(&tpg_inst2, XVIDC_CSF_YCRCB_422);
     XV_tpg_Set_bckgndId(&tpg_inst2, XTPG_BKGND_RAINBOW_COLOR);
     XV_tpg_EnableAutoRestart(&tpg_inst2);
     XV_tpg_Start(&tpg_inst2);


     Status = XV_tpg_Initialize(&tpg_inst3, XPAR_V_TPG_3_DEVICE_ID);
      if(Status!= XST_SUCCESS)
      {
      	xil_printf("TPG configuration failed\r\n");
          	return(XST_FAILURE);
      }
     XV_tpg_Set_height(&tpg_inst3, 600);
     XV_tpg_Set_width(&tpg_inst3, 800);
     XV_tpg_Set_colorFormat(&tpg_inst3, XVIDC_CSF_YCRCB_422);
     XV_tpg_Set_bckgndId(&tpg_inst3, XTPG_BKGND_DP_COLOR_RAMP);
     XV_tpg_EnableAutoRestart(&tpg_inst3);
     XV_tpg_Start(&tpg_inst3);
     xil_printf("4. TPG started!\r\n");


    /* End of TPG code*/
	xil_printf("5. Setup VTC and display mode!\r\n");


	/* Initialize the VTC driver so that it's ready to use look up
	 * configuration in the config table, then initialize it.
	 */
	vtcConfig = XVtc_LookupConfig(XPAR_V_TC_0_DEVICE_ID);
	/* Checking Config variable */
	if (NULL == vtcConfig) {
		return (XST_FAILURE);
	}
	Status = XVtc_CfgInitialize(&vtc, vtcConfig, vtcConfig->BaseAddress);
	/* Checking status */
	if (Status != (XST_SUCCESS)) {
		return (XST_FAILURE);
	}

	XVtc_ConvVideoMode2Timing(&vtc,XVTC_VMODE_SVGA,&XVtc_Timingconf);
	xil_printf("6. VTC and display mode setup complete.!\r\n");

	/***********************************************************************************************/

	XGpio_DiscreteClear(&gpio0, 1, 1);		// Clear output (LOW)
	usleep(30000);
	XGpio_DiscreteSet(&gpio0, 1, 1);

   	xil_printf("7. Mixer Configuration. \n\r");

    Status = XVMix_Initialize(&xv_mixl2, XPAR_XV_MIX_0_DEVICE_ID);

	if(Status != XST_SUCCESS) {
		xil_printf("ERR:: Mixer device not found\r\n");
		return(XST_FAILURE);
		}

	XVidC_VideoStream 	VidStrm;
	XVidC_ColorFormat Cfmt;
	XVidC_VideoTiming const *TimingPtr;

	u32 				width, height;

//	XVidC_VideoWindow Win_Layer0;
//	XVidC_VideoWindow Win_Layer1;
//	XVidC_VideoWindow Win_Layer2;
//	XVidC_VideoWindow Win_Layer3;
//
//	u32 Stride_Layer0;
//	u32 Stride_Layer1;
//	u32 Stride_Layer2;
//	u32 Stride_Layer3;


	width = 800;
	height = 600;
	//Stop mixer
	XVMix_Stop(&xv_mixl2);
	XVMix_GetLayerColorFormat(&xv_mixl2, XVMIX_LAYER_MASTER, &Cfmt);


	VidStrm.VmId = XVIDC_VM_SVGA_60_P;
	VidStrm.ColorFormatId = XVIDC_CSF_YCRCB_422;
	VidStrm.FrameRate = XVIDC_FR_60HZ;
	VidStrm.IsInterlaced = FALSE;
	VidStrm.Is3D = FALSE;
	VidStrm.ColorDepth = XVIDC_BPC_8;
	VidStrm.PixPerClk = XVIDC_PPC_1;
	VidStrm.Timing.HActive = width;
	VidStrm.Timing.VActive = height;
	XVMix_SetVidStream(&xv_mixl2, &VidStrm);

    TimingPtr 				= XVidC_GetTimingInfo(VidStrm.VmId);
    VidStrm.Timing 		 	= *TimingPtr;
    VidStrm.FrameRate 	 	= XVidC_GetFrameRate(VidStrm.VmId);

    xil_printf("\r\n********************************************\r\n");
    xil_printf("V-Mixer Input Video Stream: %s (%s)\r\n", XVidC_GetVideoModeStr(VidStrm.VmId), XVidC_GetColorFormatStr(VidStrm.ColorFormatId));
    xil_printf("Frame Rate: %s\r\n",  XVidC_GetFrameRateStr(VidStrm.VmId));
    xil_printf("Pixel Clock: %d\r\n", XVidC_GetPixelClockHzByVmId(VidStrm.VmId));
    xil_printf("Color Depth: %d\r\n", VidStrm.ColorDepth);

 	xil_printf("HSYNC Timing: hav=%04d, hfp=%02d, hsw=%02d(hsp=%d), "
 			"hbp=%03d, htot=%04d \r\n", VidStrm.Timing.HActive,
			VidStrm.Timing.HFrontPorch, VidStrm.Timing.HSyncWidth,
			VidStrm.Timing.HSyncPolarity,
			VidStrm.Timing.HBackPorch, VidStrm.Timing.HTotal);
 	xil_printf("VSYNC Timing: vav=%04d, vfp=%02d, "
 		"vsw=%02d(vsp=%d), vbp=%03d, vtot=%04d\r\n",
		VidStrm.Timing.VActive, VidStrm.Timing.F0PVFrontPorch,
		VidStrm.Timing.F0PVSyncWidth, VidStrm.Timing.VSyncPolarity,
		VidStrm.Timing.F0PVBackPorch, VidStrm.Timing.F0PVTotal);
     xil_printf("********************************************\r\n");

 	/* Set Memory Layer Base Addresses */
 	int NumLayers = XVMix_GetNumLayers(&xv_mixl2);
 	xil_printf("\nNumLayers: %d\n", NumLayers);


//
//	Win_Layer1.StartX = 0;
//	Win_Layer1.StartY = 0;
//	Win_Layer1.Width = 400;
//	Win_Layer1.Height = 300;
//	Stride_Layer1 = 0;
//
//	Win_Layer1.StartX = 400;
//	Win_Layer1.StartY = 0;
//	Win_Layer1.Width = 400;
//	Win_Layer1.Height = 300;
//	Stride_Layer1 = 0;
//
//	Win_Layer1.StartX = 0;
//	Win_Layer1.StartY = 300;
//	Win_Layer1.Width = 300;
//	Win_Layer1.Height = 300;
//	Stride_Layer1 = 0;
//
//	Win_Layer1.StartX = 400;
//	Win_Layer1.StartY = 300;
//	Win_Layer1.Width = 400;
//	Win_Layer1.Height = 300;
//	Stride_Layer1 = 0;
//
//	XVMix_SetLayerWindow(&xv_mixl2, XVMIX_LAYER_MASTER, &Win_Layer1, Stride_Layer1);
//	XVMix_SetLayerWindow(&xv_mixl2, XVMIX_LAYER_1, &Win_Layer1, Stride_Layer1);
//	XVMix_SetLayerWindow(&xv_mixl2, XVMIX_LAYER_2, &Win_Layer1, Stride_Layer1);
//	XVMix_SetLayerWindow(&xv_mixl2, XVMIX_LAYER_3, &Win_Layer1, Stride_Layer1);


	//XVMix_SetBackgndColor(&xv_mixl2, XVMIX_BKGND_BLUE, XVIDC_BPC_8);
	XVMix_SetBackgndColor(&xv_mixl2, XVMIX_BKGND_BLUE, VidStrm.ColorDepth);
	XVMix_LayerDisable(&xv_mixl2, XVMIX_LAYER_ALL);

// 	XVMix_MoveLayerWindow(&xv_mixl2,XVMIX_LAYER_MASTER,0,0);
 	XVMix_MoveLayerWindow(&xv_mixl2,XVMIX_LAYER_1,400,0);
 	XVMix_MoveLayerWindow(&xv_mixl2,XVMIX_LAYER_2,0,300);
 	XVMix_MoveLayerWindow(&xv_mixl2,XVMIX_LAYER_3,400,300);

//	XVMix_SetLayerAlpha(&xv_mixl2, XVMIX_LAYER_MASTER, 10);

	XVMix_LayerEnable(&xv_mixl2, XVMIX_LAYER_MASTER);
	XVMix_LayerEnable(&xv_mixl2, XVMIX_LAYER_1);
	XVMix_LayerEnable(&xv_mixl2, XVMIX_LAYER_2);
	XVMix_LayerEnable(&xv_mixl2, XVMIX_LAYER_3);

	XVMix_Start(&xv_mixl2);
	xil_printf("INFO: Mixer configured\r\n");
	usleep(1000);
	XVMix_DbgReportStatus(&xv_mixl2);

	XVMix_DbgLayerInfo(&xv_mixl2,XVMIX_LAYER_MASTER);

   	xil_printf("8. Mixer configured. \n\r");

	XVMix_InterruptDisable(&xv_mixl2);
	XVMix_Start(&xv_mixl2);
	xil_printf("\nINFO: Mixer configured\r\n");

	XVMix_DbgReportStatus(&xv_mixl2); // DEBUG TODO AS

	xil_printf("Enabled %d \r\n",    XVMix_IsLayerEnabled(&xv_mixl2,XVMIX_LAYER_MASTER));

	XVMix_DbgReportStatus(&xv_mixl2);
	XVMix_DbgLayerInfo(&xv_mixl2,XVMIX_LAYER_MASTER);
   	xil_printf("9. Mixer started. \n\r");
	while(1);


    cleanup_platform();
    return 0;
}

 

 

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Teacher drjohnsmith
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Re: ZYNQ Video Mixer design

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work from the output .

You are not worried by data at this time, just the stream control lines,

 

Put the ILA on the AXI stream controls and back pressure lines of the output.

See if they are  stopping the data comming forward,

If they are, find out why,

    if they arnt, move back one

 

and repeat.

 

When the controls all work, you will have data flowing through

  only then look at the screen,

 

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Re: ZYNQ Video Mixer design

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Hello @drjohnsmith ,

 

It does not look like the HW is the issue. Timing is also correct from the reported debug output.The issue looks seems to be the configuration of the mixer with streaming inputs.

The ILA outputs for both input and outpiut of mixer are below and I can clearly see that TLAST, TVALID, TREADY and TUSER transitions both on the input and output side.

ila1_v.pngila2.png

When I use the code above the screen output is blank.

When I use the code below using the low level API the master layer shows up on screen but the mixer debug call reports that the control register has a wrong value and yet I see the TPG pattern on screen. This looks like a bug with the IP to me.

 

 

int main()
{
	int Status;
    init_platform();

    print("TPG application on ZC702 using on-board HDMI\n\r");

    //Configure the PS IIC Controller
    ps_iic_init(XPAR_XIICPS_0_DEVICE_ID, &IicPs_inst);

    // Set the iic mux to the ADV7511
    set_iic_mux(&IicPs_inst, ZC702_I2C_SELECT_HDMI, ZC702_I2C_MUX_ADDR);
    print("HDMI IIC configured\n\r");

    //Wait for the monitor to be connected
    wait_for_monitor(&IicPs_inst, ZC702_HDMI_ADDR);

    // ADV7511 Basic Configuration
    configure_adv7511(&IicPs_inst,ZC702_HDMI_ADDR);
    // ADV7511 ZC702 Specific configuration
    configure_adv7511_zc702(&IicPs_inst,ZC702_HDMI_ADDR);

    xil_printf("HDMI Setup Complete!\r\n");

    xil_printf("TPG1 setup!\r\n");

    /* Insert the code for the TPG here */
    Status = XV_tpg_Initialize(&tpg_inst, XPAR_V_TPG_0_DEVICE_ID);
    if(Status!= XST_SUCCESS)
    {
    	xil_printf("TPG configuration failed\r\n");
        	return(XST_FAILURE);
    }

    // Set Resolution to 800x600
    XV_tpg_Set_height(&tpg_inst, 600);
    XV_tpg_Set_width(&tpg_inst, 800);

    // Set Color Space to YUV422
    XV_tpg_Set_colorFormat(&tpg_inst, XVIDC_CSF_YCRCB_422);

    //Start the TPG
    XV_tpg_EnableAutoRestart(&tpg_inst);
    XV_tpg_Start(&tpg_inst);
    xil_printf("TPG started!\r\n");

    // Change the pattern to color bar
    XV_tpg_Set_bckgndId(&tpg_inst, XTPG_BKGND_CHECKER_BOARD);

    //Start the TPG
    // Set Overlay to moving box
    // Set the size of the box
    XV_tpg_Set_boxSize(&tpg_inst, 50);
    // Set the speed of the box
    XV_tpg_Set_motionSpeed(&tpg_inst, 5);
    // Enable the moving box
    XV_tpg_Set_ovrlayId(&tpg_inst, 1);

    /* End of TPG code*/

    xil_printf("TPG2 setup!\r\n");

	xil_printf(" Setup VTC and display mode Complete!\r\n");

    Display();
	
   	xil_printf("/* Mixer Configuration               */\n\r");



    XVMix_DbgReportStatus(&xv_mixl2);

    xv_config = XV_mix_LookupConfig(XPAR_XV_MIX_0_DEVICE_ID);
    XV_mix_CfgInitialize(&xv_mix,xv_config,xv_config->BaseAddress);


    XV_mix_Set_HwReg_width(&xv_mix, (u32)800);
    XV_mix_Set_HwReg_height(&xv_mix, (u32) 600);
    XV_mix_Set_HwReg_layerEnable(&xv_mix,(u32)7);


//	XV_mix_Set_HwReg_layerStartX_0(&xv_mix,(u32)0);
//	XV_mix_Set_HwReg_layerStartY_0(&xv_mix,0);
//	XV_mix_Set_HwReg_layerWidth_0(&xv_mix,(u32)800);
//	XV_mix_Set_HwReg_layerHeight_0(&xv_mix,(u32)600);
//	XV_mix_Set_HwReg_layerAlpha_0(&xv_mix, 255);
//
//	XV_mix_Set_HwReg_layerStartX_1(&xv_mix,400);
//	XV_mix_Set_HwReg_layerStartY_1(&xv_mix,0);
//	XV_mix_Set_HwReg_layerWidth_1(&xv_mix,(u32)400);
//	XV_mix_Set_HwReg_layerHeight_1(&xv_mix,(u32)300);
//	XV_mix_Set_HwReg_layerAlpha_1(&xv_mix, 255);
//
//	XV_mix_Set_HwReg_layerStartX_2(&xv_mix,0);
//	XV_mix_Set_HwReg_layerStartY_2(&xv_mix,0);
//	XV_mix_Set_HwReg_layerWidth_2(&xv_mix,(u32)400);
//	XV_mix_Set_HwReg_layerHeight_2(&xv_mix,(u32)300);
//	XV_mix_Set_HwReg_layerAlpha_2(&xv_mix, 255);

   	xil_printf("/* Mixer configured               */\n\r");

	XV_mix_EnableAutoRestart(&xv_mix);
	XV_mix_Start(&xv_mix);

	XVMix_Initialize(&xv_mixl2,XPAR_XV_MIX_0_DEVICE_ID);
	XVMix_DbgReportStatus(&xv_mixl2);

	XVMix_DbgLayerInfo(&xv_mixl2,0);
//	XVMix_DbgLayerInfo(&xv_mixl2,1);
//	XVMix_DbgLayerInfo(&xv_mixl2,2);
   	xil_printf("/* Mixer started               */\n\r");

	while(1);


    cleanup_platform();
    return 0;
}

 

 

Teacher drjohnsmith
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Re: ZYNQ Video Mixer design

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well done, thats good debugging,
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Re: ZYNQ Video Mixer design

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@drjohnsmith 

I  don't see how to get around this though. Why do the the examples only support buffered layers.

 

 

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Re: ZYNQ Video Mixer design

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On Vivado 2018.3 when importing the example on chapter 5 of the LogicCore PG there are a bunch of errors generated. Not sure if this has been fixed on the latest version.

The only difference from the design shown above is the use of a GPIO for resetting the IP. Seems like the Vmixer Ip is sensirtive to the dimensions of the input feeds streams.1.png

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Re: ZYNQ Video Mixer design

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Hi @dimiter,

 

I have a design working on the ZCU102 and will update it to test streaming layers.

 

As far as building the example design on 2018.3, I am not aware of any issue. I will double check this on my side as well.

 

 

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Re: ZYNQ Video Mixer design

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Hi @samk 

 

If it helps, I have attached the hardware for ZC702 with 4 TPG.

 

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Re: ZYNQ Video Mixer design

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Hi @dimiter,

 

I apologize for the delay.

 

I built ZC702 project where I have 3 MM layers and 1 streaming layer and I don't see any issue. 

One note is that the TPG for the streaming layer is set to match the dimensions in the VMIX. These need to match.

 

Please see the attached project and let me know if you have any questions. Based on this project, I don't see an issue with the streaming interface.

 

helloworld.c is the main source.

 

 

 

 

 

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Re: ZYNQ Video Mixer design

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Hi @dimiter 

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply).

 

If this is not solved/answered, please reply in the topic giving more information on your current status.

 

Thanks and Regards,

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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Re: ZYNQ Video Mixer design

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Hi @samk and @aoifem ,

Sorry for the delayed response.

I tested the design uploaded above on a ZC702 board with Vivado 2018.3 and it does not work. I had to change the mixer version to V3.0 from V4.0.

 

I will upload ILA snbapshots later.

The .tcl file above contains 2 streaming layers and 3 MM layers.

The SDK files contains an error since the logo has not been enabled. When commenting those section on the attched c file and running the design the System ILA at the mixer output shows no data.

 

I wanted to use only 4 streaming layers to implement somthing similar to this:

https://forums.xilinx.com/t5/Xcell-Daily-Blog-Archived/Adam-Taylor-s-MicroZed-Chronicles-Part-223-Video-Mixing-with-the/ba-p/806149

So I would say I'm at the same point whereI was 2 months ago.

I think it would be easier coming up with a custom verilog code at this point.

 

 

 

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Re: ZYNQ Video Mixer design

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Hi @dimiter,

 

The project was built for 2019.1 which is likely where your errors are coming from. There should have been a warning/notification when running the TCL script to let you know that it was built with 2019.1.

 

The issue you are pointing out seems to be that streaming layers do not work. I have verified on my side that there is no issue with streaming layers.

The design I sent can be updated for 4 SS layers fairly easily, and I don't expect to see an issue here either.

That being the case, it seems like you are setting up the mixer incorrectly on your side. To help move you forward, I suggest using the project I provided or the example design as a starting point and replacing your code or if you want to continue with what you have so far, please post more details here on what you are experiencing on your side. (Including ILAs as you previously mentioned)

 

Thanks,

Sam

 

As a note, the tcl script configures the v_mix as version 4.0.

# Create instance: v_mix_0, and set properties
set v_mix_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:v_mix:4.0 v_mix_0 ]
set_property -dict [ list \
CONFIG.AXIMM_DATA_WIDTH {64} \
CONFIG.C_M_AXI_MM_VIDEO1_DATA_WIDTH {64} \
CONFIG.C_M_AXI_MM_VIDEO2_DATA_WIDTH {64} \
CONFIG.C_M_AXI_MM_VIDEO3_DATA_WIDTH {64} \
CONFIG.C_M_AXI_MM_VIDEO4_DATA_WIDTH {64} \
CONFIG.C_M_AXI_MM_VIDEO5_DATA_WIDTH {64} \
CONFIG.C_M_AXI_MM_VIDEO6_DATA_WIDTH {64} \
CONFIG.C_M_AXI_MM_VIDEO7_DATA_WIDTH {64} \
CONFIG.C_M_AXI_MM_VIDEO8_DATA_WIDTH {64} \
CONFIG.LAYER4_INTF_TYPE {1} \
CONFIG.LAYER4_VIDEO_FORMAT {2} \
CONFIG.NR_LAYERS {5} \
CONFIG.SAMPLES_PER_CLOCK {1} \
CONFIG.VIDEO_FORMAT {2} \
] $v_mix_0

 

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Re: ZYNQ Video Mixer design

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Hi @samk 

Looks like the .tcl file you have uploaded has an issue with the AXIS subset converter. I don't understand how this can happen.

Can you confirm the setting for this IP below? Below are the details.

 

I installed Vivado 2019.3. when I source the .tcl file  (source ./ZC702_HDMI.tcl) I get the following errors.

ERROR: [IP_Flow 19-3478] Validation failed for parameter 'TID Remap String(TID_REMAP)' with value 'tid[0:0]' for BD Cell 'axis_subset_converter_0'. tid remap string must be 1'b0 if MI tid width is 0
ERROR: [IP_Flow 19-3478] Validation failed for parameter 'TDEST Remap String(TDEST_REMAP)' with value 'tdest[0:0]' for BD Cell 'axis_subset_converter_0'. tdest remap string must be 1'b0 if MI tdest width is 0
ERROR: [IP_Flow 19-3478] Validation failed for parameter 'TLAST Remap String(TLAST_REMAP)' with value 'tlast[0]' for BD Cell 'axis_subset_converter_0'. tlast remap string must be 1'b0 if MI tlast width is 0
ERROR: [IP_Flow 19-3478] Validation failed for parameter 'TUSER Remap String(TUSER_REMAP)' with value 'tuser[0:0]' for BD Cell 'axis_subset_converter_0'. tuser remap string must be constant if SI or MI tuser width is 0
ERROR: [IP_Flow 19-3478] Validation failed for parameter 'TKEEP Remap String(TKEEP_REMAP)' with value 'tkeep[1:0]' for BD Cell 'axis_subset_converter_0'. tkeep remap string must be 1'b0 if MI tkeep width is 0
ERROR: [IP_Flow 19-3478] Validation failed for parameter 'TSTRB Remap String(TSTRB_REMAP)' with value 'tstrb[1:0]' for BD Cell 'axis_subset_converter_0'. tstrb remap string must be 1'b0 if MI tstrb width is 0
INFO: [IP_Flow 19-3438] Customization errors found on 'axis_subset_converter_0'. Restoring to previous valid configuration.
INFO: [Common 17-17] undo 'set_property'
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

    while executing
"rdi::add_properties -dict {CONFIG.M_TDATA_NUM_BYTES 2 CONFIG.S_TDATA_NUM_BYTES 3 CONFIG.TDATA_REMAP {tdata[15:0]} CONFIG.TDEST_REMAP {tdest[0:0]} CONF..."
    invoked from within
"set_property -dict [ list  CONFIG.M_TDATA_NUM_BYTES {2}  CONFIG.S_TDATA_NUM_BYTES {3}  CONFIG.TDATA_REMAP {tdata[15:0]}  CONFIG.TDEST_REMAP {tdest[0:0..."
    (procedure "create_root_design" line 61)
    invoked from within
"create_root_design """
    (file "./ZC702_HDMI.tcl" line 906)

 

Then I tried changing the "set scripts_vivado_version 2018.3" and downgraded the video mixer to Verison 3.0.

I get the same error for the AXIS subset converter.

 

 

I ended adding an AXIS subset converter manually and wired it by issuing commands from the tcl file.

And here lies the main discrepancy.

The .tcl file uploaded by @samk has this configuration for the AXIS subset converter:

 set axis_subset_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_subset_converter_0 ]
  set_property -dict [ list \
   CONFIG.M_TDATA_NUM_BYTES {2} \
   CONFIG.S_TDATA_NUM_BYTES {3} \
   CONFIG.TDATA_REMAP {tdata[15:0]} \
   CONFIG.TDEST_REMAP {tdest[0:0]} \
   CONFIG.TID_REMAP {tid[0:0]} \
   CONFIG.TKEEP_REMAP {tkeep[1:0]} \
   CONFIG.TLAST_REMAP {tlast[0]} \
   CONFIG.TSTRB_REMAP {tstrb[1:0]} \
   CONFIG.TUSER_REMAP {tuser[0:0]} \
 ] $axis_subset_converter_0

This clearly gives errors on all Vivado versions.

In the current design I set it to this configuration.

  set axis_subset_converter_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 axis_subset_converter_0 ]
  set_property -dict [ list \
   CONFIG.M_HAS_TKEEP {1} \
   CONFIG.M_HAS_TLAST {1} \
   CONFIG.M_HAS_TSTRB {1} \
   CONFIG.M_TDATA_NUM_BYTES {2} \
   CONFIG.M_TDEST_WIDTH {0} \
   CONFIG.M_TID_WIDTH {0} \
   CONFIG.M_TUSER_WIDTH {1} \
   CONFIG.S_HAS_TKEEP {1} \
   CONFIG.S_HAS_TLAST {1} \
   CONFIG.S_HAS_TSTRB {1} \
   CONFIG.S_TDATA_NUM_BYTES {3} \
   CONFIG.S_TDEST_WIDTH {0} \
   CONFIG.S_TID_WIDTH {0} \
   CONFIG.S_TUSER_WIDTH {1} \
   CONFIG.TDATA_REMAP {tdata[15:0]} \
   CONFIG.TKEEP_REMAP {tkeep[1:0]} \
   CONFIG.TLAST_REMAP {tlast[0]} \
   CONFIG.TSTRB_REMAP {tstrb[1:0]} \
   CONFIG.TUSER_REMAP {tuser[0:0]} \
 ] $axis_subset_converter_0

2.png

 

Even with this change the two ILA's report the following

 

3_ila1.png4_ila2.png

 

 

So I have the following question if you can please address them:

 

 a) For multiple AXIS sources with only VALID, READY, DATA, TUSER and TLAST the mixer will not work? Is that correct, 

Can you confirm that it needs the TSTRB and TKEEP signals?

b) If the 4 TPG's are configured with a resolution of 640x480 can I use the scaling features of the mixer to output all 4 of them in a 800x600 output resolution or do I need a separate scaler. You meantion above that the mixer resolution should match the source resolution??

 

 

 

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Re: ZYNQ Video Mixer design

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Hi @dimiter,

 

I can double check the .tcl file. I am using the released version of 2019.1 with no AR's, so this should be the same tool you are using.

 

 a) For multiple AXIS sources with only VALID, READY, DATA, TUSER and TLAST the mixer will not work? Is that correct, 

Can you confirm that it needs the TSTRB and TKEEP signals?

 

SK - I don't believe that these are necessary. The Stream should follow that defined UG934.

b) If the 4 TPG's are configured with a resolution of 640x480 can I use the scaling features of the mixer to output all 4 of them in a 800x600 output resolution or do I need a separate scaler. You meantion above that the mixer resolution should match the source resolution??

SK - The RX of the mixer should match the source resolution. The mixer needs to be configured to receive the resolution that the source is sending. So in your case, the mixer needs to be set to 640x480 for the streaming RX interface.

 

Scaling is supported per layer, but this is done after the RX is received. 

 

 

 

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Re: ZYNQ Video Mixer design

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Hi @dimiter 

 

Can you update your status on this? 

If your issue has been resolved can you share the solution with the community? 

 

Regards, 

Aoife
Product Application Engineer - Xilinx Technical Support EMEA
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Re: ZYNQ Video Mixer design

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HI @dimiter,

 

You are right, the TCL script is having issues on my side as well. I will rebuild from scratch for 2019.1.

However, you were reporting that streaming interfaces do not work with the video mixer and I have tested sucessfully that it does work. This means that there is likely a size mismatch on your side as mentioned previously.

 

Please let us know your status and I am happy to assist.

 

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Re: ZYNQ Video Mixer design

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Hi @aoifem  and @samk ,

 

I have not been able to get it working. The code shared by @samk above hangs during configuration. (INFO: TPG configured (%d x %d)(%d)\r\n).

and there is no stream present at all when checking witht the ILA.

 

So I started from scratch with a design using a single TPG connected directly to AXIS video out with a VTC configured for 800x600with no mixer based on code from @florentw . That works.

Then I insert a mixer and an AXI subset converter. The reset of the TPG, Mixer and aXIS vidoe out is connected to a GPIO.

The idea is to use the mixer as a passthrough device. Even a simple case like this does not work correctly. After the TPG and VTC are setup I am able however to crash the mixer by issuing the following:

    XVMix_DbgReportStatus(&xv_mixl2);

    xv_config = XV_mix_LookupConfig(XPAR_XV_MIX_0_DEVICE_ID);
    XV_mix_CfgInitialize(&xv_mix,xv_config,xv_config->BaseAddress);


    XV_mix_Set_HwReg_width(&xv_mix, (u32)800);
    XV_mix_Set_HwReg_height(&xv_mix, (u32) 600);
    XV_mix_Set_HwReg_layerEnable(&xv_mix,(u32)7);

	XV_mix_EnableAutoRestart(&xv_mix);
	XV_mix_Start(&xv_mix);

	XVMix_Initialize(&xv_mixl2,XPAR_XV_MIX_0_DEVICE_ID);
	XVMix_DbgReportStatus(&xv_mixl2);

	XVMix_DbgLayerInfo(&xv_mixl2,0);
   	xil_printf("/* Mixer started               */\n\r");

This causes the memory map of the video mixer to some wrong value .

 

----->MIXER STATUS<----
Pixels Per Clock: 0
Color Depth:      0
Number of Layers: 0
Control Reg:      0x1D773C69

 

 

 

 

PART II

 

Next step was augmenting the mixer with 3 more TPG's and ILA. The mixer streaming layers are setup with global alpha and scaling to allow scaling the 4 streams 800x600 streams to a 1/4 so that they can fit on the 800x600 main screen.

 

1.png2.png3.png4.png

When I run the attached SDK code , I'm not able to output anything on screen. If I run the snippet of code above, then the mixer hardware somehow misbehaves and only outputs the master layer only.

 

So based on this I can infer that the IP is buggy.

I also tried using the code from @adamTaylor . He uses the low level API. This also does not work. Either the HSL mixer IP memory map has changed since he posted the example or somehting else is going on.

I have searched all the app-notes for a simple example that uses at least two stremaing layers and I have not been able to find any.

I have attched the tcl file and application code of the code that "crashes" the IP as well as the code that is supposed to work.

The idea was to use at least two or 4 TPG to output all of them simulatenously on one screen.

 

Xilinx has a video showing this with an optical flow demo but they have not released any example code.

 

I thought I would be able to scale the 4 streaming layers and tile them on a single screen.

Maybe I shoudl ask if the mixer is able to do this in the first place.

 

So can you release an example on

a) how to setup the mixer using layer 2 API for a single layer at least

b) scale two or 4 streaming layer so that they fit in a single screen.

 

 

==UPDATE==

I checked the input and output ILA and I can see there is data on the AXIS bus. So I thought about this and based on the above architecture I have the follwoing questions:

 

a) Each stream needs a window to be defined. What about the master layer. Every time I define a window on that it hangs?

b) If I want to scale the incoming 800x600 streams to half the resolution I use the set scale Layer 2 API. Why it does not work?

c)  Running the attached code you get the follwoing debug output but no imageon screen

 

7. Mixer Configuration. 

NumLayers: 4
INFO: Mixer configured


----->MIXER STATUS<----
Pixels Per Clock: 1
Color Depth:      8
Number of Layers: 4
Control Reg:      0x81
Layer Enable Reg: 0xF

Layer Master: Enabled
Layer 1     : Enabled
Layer 2     : Enabled
Layer 3     : Enabled
Layer 4     : Disabled
Layer 5     : Disabled
Layer 6     : Disabled
Layer 7     : Disabled
Layer 8     : Disabled
Layer 9     : Disabled
Layer 10     : Disabled
Layer 11     : Disabled
Layer 12     : Disabled
Layer 13     : Disabled
Layer 14     : Disabled
Layer Logo  : Disabled

Background Color Y/R: 0
Background Color U/G: 0
Background Color V/B: 255

8. Mixer configured. 

Enabled 1 


----->Master Layer Status<----
State: Enabled
Color Format: YUV_422

Resolution: 800 x 600
Stream Info->
	Color Format:     YUV_422
	Color Depth:      8
	Pixels Per Clock: 1
	Mode:             Progressive
	Frame Rate:       60Hz
	Resolution:       800x600@60Hz
	Pixel Clock:      39790080


----->Layer 1 Status<----
State: Enabled
Type : Stream
Addr : 0x0
Chroma Addr : 0x0
Alpha: 0
Scale: 1x
Color Format: YUV_422

Window Data: 
   Start X    = 400
   Start Y    = 0
   Win Width  = 400
   Win Height = 300
   Win Stride = 0


----->Layer 2 Status<----
State: Enabled
Type : Stream
Addr : 0x0
Chroma Addr : 0x0
Alpha: 0
Scale: 1x
Color Format: YUV_422

Window Data: 
   Start X    = 0
   Start Y    = 300
   Win Width  = 300
   Win Height = 300
   Win Stride = 0


----->Layer 3 Status<----
State: Enabled
Type : Stream
Addr : 0x0
Chroma Addr : 0x0
Alpha: 0
Scale: 1x
Color Format: YUV_422

Window Data: 
   Start X    = 400
   Start Y    = 300
   Win Width  = 400
   Win Height = 300
   Win Stride = 0
9. Mixer running. 

 

 

 

 

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Re: ZYNQ Video Mixer design

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HI @dimiter,

 

I ran on my side, and let's start with (c). A good point when debugging any system is to start with getting the simplest thing working and then moving to a more complicated system.

Because we are using a monitor as a pass/fail, (c - why is the monitor blank) is where we can start.

I edited your code to remove anything but the master layer. This really means that the Video Mixer is acting as a pass-through design to start. We can use this to verify the rest of your setup.

Doing this, I don't see DS19 locked.  

Next, working backward, I checked the ILA from the Video Mixer to the subset converter (connected to the AXI-4 Video Bridge).

You can see that TREADY is cycling. This is usually an indicator of backpressure and that an incorrect resolution is being sent to the next IP.

2019-10-02 21_59_18-xcoapps55_6 (xcoapps55_6 (samk)) - VNC Viewer.png

Next, I wanted to see what horizontal resolution is being sent from the Video Mixer. To do this I restarted the project and set an ILA for TVALID=1. I make sure to trigger the ILA before starting the application. This should capture the first line of the first frame out of the core.

It did capture the first line of the first frame. It showed 800clocks of video data between TUSER and TLAST. 

2019-10-02 22_08_45-xcoapps55_6 (xcoapps55_6 (samk)) - VNC Viewer.png

 

 

If we assume that height (lines) matches correctly, then there is another issue. Here is what I would check:

  1. VTC configuration
    1. put an ILA on the output of the VTC.
  2. Is there an issue with the configuration of the AXI4-Stream to Video Out core?
    1. Monitor the overflow/underflow/status outputs from the core.

Regards,

Sam

 

 

 

 

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Re: ZYNQ Video Mixer design

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Hi @dimiter,

 

Also here is the updated TCL script for 2019.1. There is an issue with the tcl commands for one of the IP that is a known issue found and a fix request has been filed by @florentw

 

 

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Re: ZYNQ Video Mixer design

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Hi @samk ,

 

I modified the VTC to output a fixed 800x600 resolution.

I can get ONLY the Master layer to show up on screen. However all the API clls I used to enable the other layers are not succesful.

 

You meantioned that all streaming layers should have the same resolution.

Just wondering if this is correct since the timing and resolution would not be met. I tried to scale the other layers and the API calls FAILS.

Basically:

a) I set up windows for each layer and set their location on screen apart from MASTER layer since this hangs.

b) Then I enable scaling by 2x. I assume this means downscaling since the API is not clear.

c) I then enable the layers.

 

Debug window shows that the windows are set but only master layer 1 shows up on screen.

I can confirm that all the TPG's output data so this looks like a Mixer issue.

 

I also tried the example from Adam Taylor, he uses the lower level API below Layer 2. This also does not work.

 

//XV_mix_Set_HwReg_width(&xv_mix, (u32)800);
//XV_mix_Set_HwReg_height(&xv_mix, (u32) 600);
//XV_mix_Set_HwReg_layerEnable(&xv_mix,(u32)0x07);
//
//
//XV_mix_Set_HwReg_layerStartX_0(&xv_mix,(u32)0);
//XV_mix_Set_HwReg_layerStartY_0(&xv_mix,0);
//XV_mix_Set_HwReg_layerWidth_0(&xv_mix,(u32)400);
//XV_mix_Set_HwReg_layerHeight_0(&xv_mix,(u32)300);
//XV_mix_Set_HwReg_layerAlpha_0(&xv_mix, 255);
//
//XV_mix_Set_HwReg_layerStartX_1(&xv_mix,400);
//XV_mix_Set_HwReg_layerStartY_1(&xv_mix,300);
//XV_mix_Set_HwReg_layerWidth_1(&xv_mix,(u32)400);
//XV_mix_Set_HwReg_layerHeight_1(&xv_mix,(u32)300);
//XV_mix_Set_HwReg_layerAlpha_1(&xv_mix, 255);
//
//XV_mix_Set_HwReg_layerStartX_2(&xv_mix,400);
//XV_mix_Set_HwReg_layerStartY_2(&xv_mix,0);
//XV_mix_Set_HwReg_layerWidth_2(&xv_mix,(u32)400);
//XV_mix_Set_HwReg_layerHeight_2(&xv_mix,(u32)300);
//XV_mix_Set_HwReg_layerAlpha_2(&xv_mix, 255);
//
//XV_mix_Set_HwReg_layerStartX_3(&xv_mix,0);
//XV_mix_Set_HwReg_layerStartY_3(&xv_mix,300);
//XV_mix_Set_HwReg_layerWidth_3(&xv_mix,(u32)400);
//XV_mix_Set_HwReg_layerHeight_3(&xv_mix,(u32)300);
//XV_mix_Set_HwReg_layerAlpha_3(&xv_mix, 255);
//
//XV_mix_EnableAutoRestart(&xv_mix);
//XV_mix_Start(&xv_mix);

 

a) Can you provide an example or hint for at least two streaming layers using either layer 2 or the low level API? I noticed that Master layer scaling , alpha, and resizing API calls are not supported and they cause it to freeze.

b) Would I be correct to assume that the Master layer shoudl have a resolution of 1640x1200 to accomodate this design as opposed to 800x600 for the other streams? Maybe I misunderstood what was suggested above.

 

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Re: ZYNQ Video Mixer design

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Hi @samk,

 

Just to confirm, the information above is incorrect. The master layer should match the resolution of the frame , the rest of the layers can have different resolutions.

Althoutgh it's flakey sometimes it works for 1 sec and then the video feed abruptly cuts off.

 

The following issues were parts of the resolution:

a) enable all the sources prior to enabling the mixer (meantioned in the PG)

b) use an external GPIO reset ( not meantioned)

c) check correctness of window settings for each stream.

 

 

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Re: ZYNQ Video Mixer design

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Hi @dimiter,

 

I am glad you were able to figure out the issue. I will check that a hard GPIO reset is required and if so, will file for edits to the PG.

  • Flush command is used
  • A video streaming layer is used, then enabled long before data is available. This can cause the mixer to freeze. In this situation, apply a hard reset once data is available.

 

 

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Re: ZYNQ Video Mixer design

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Hi @samk  and @florentw ,

 

There is another bug with the streaming setup. This is using 2018.3 and mixer IP V3.0.  Not sure if it has been fixed on V4.0.

I have not tested witht the memory mapped layers.

Assuming you have a window that is close to the edge you get a 0x1000 (4096 response ) even though the window is within the master layer boundary and respects the location on multiples of 8.

DId the author butcher the  boundary case on the SDK layer?

 

  WinResInRange = ((Win->Width > (XVMIX_MIN_STRM_WIDTH-1)) && (Win->Height > (XVMIX_MIN_STRM_HEIGHT-1)) && (Win->Width < MixPtr->Config.LayerMaxWidth[LayerId-1]) && (Win->Height <= MixPtr->Config.MaxHeight)); 
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