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Observer merlyn
Observer
860 Views
Registered: ‎07-19-2018

Zynq MPSoC Displayport Lane Reversal

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Is it possible to recover in software from reversing display port lane order? I have a prototype board where displayport connector lanes 0-3 are wired to GTR TX lanes 3-0 respectively. I'm looking at UG1085 pg 926 Fig 33-1 and it seems to imply that only lanes 0,1 are to be used. Thanks.

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Moderator
Moderator
791 Views
Registered: ‎11-09-2015

Re: Zynq MPSoC Displayport Lane Reversal

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Hi @watari,

I believe @merlyn is talking about the DP controller from the PS as he is talking about the PS GTR and pointing to the UG1085.

 

@merlyn,

As @watari correctly pointed, the harden Displayport controller of the ZynqUS+ devices is using only 2 lanes. This is the reason why it can only go up to 4K@30 and not 4K@60.

However, if you look at UG1085 (table 29-1) it might be confusing as you can see 4 lanes with DP:DP.JPG

 However, you can see that there is 2 times DP.0 and 2 times DP.1. This only means that there is 2 different position the 2 lanes can have. And you can see the same when configuring the ZynqMP in vivado:DP2.JPG

I do not think this is possible to swap the lanes with the DP controller, however, if you check the Zynq configuration GUI it seems that the lane are in an inverted order:

DP3.JPG

 

So according to your description, it seems that you are correctly connected (just set lane selection to Dual Higher). Only note that you can only use 2 lanes

Hope that helps,

Regards,

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
2 Replies
Scholar watari
Scholar
821 Views
Registered: ‎06-16-2013

Re: Zynq MPSoC Displayport Lane Reversal

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Hi @merlyn

 

I'm little confused. Because of Zynq MPSoC can implement/use at least two DisplayPort Tx.

There are DisplayPort Tx with PS-GTR (2 lanes) and DisplayPort Tx with PL-GTx (ex. 4 lanes).

In this case, it seems that you implement DisplayPort Tx at PL. So, maybe, you can change it by using remapper.

 

Best regards,

 

Moderator
Moderator
792 Views
Registered: ‎11-09-2015

Re: Zynq MPSoC Displayport Lane Reversal

Jump to solution

Hi @watari,

I believe @merlyn is talking about the DP controller from the PS as he is talking about the PS GTR and pointing to the UG1085.

 

@merlyn,

As @watari correctly pointed, the harden Displayport controller of the ZynqUS+ devices is using only 2 lanes. This is the reason why it can only go up to 4K@30 and not 4K@60.

However, if you look at UG1085 (table 29-1) it might be confusing as you can see 4 lanes with DP:DP.JPG

 However, you can see that there is 2 times DP.0 and 2 times DP.1. This only means that there is 2 different position the 2 lanes can have. And you can see the same when configuring the ZynqMP in vivado:DP2.JPG

I do not think this is possible to swap the lanes with the DP controller, however, if you check the Zynq configuration GUI it seems that the lane are in an inverted order:

DP3.JPG

 

So according to your description, it seems that you are correctly connected (just set lane selection to Dual Higher). Only note that you can only use 2 lanes

Hope that helps,

Regards,

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**