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Participant p.nejad
Participant
2,180 Views
Registered: ‎03-09-2018

axi4s_to_video_out won't lock

Hello,

 I'm new to FPGA and I have a project with spartan 6 and ise14.7. 

I am working on spartan 6 FPGA that is connected  to ONsemi sensor. The FPGA is also connected to  analoge device encoder to come out PAL. I have the system working without xilinx video IPs but the quality of image is not good at all ( I am not using Color correction). so  I'm trying to get it working with video proccessing IPs from xilinx to take advantage of CFA and CCM.  

 

for the first step I have just video_in_to axi4s and axi4s and axi4s_to_video_out blocks, after I get this working I will add the CFA, CCM, RGB2YCrCb.

 

I have created video_in_to axi4s and axi4s_to_video_out with VTC to create 756p timing. I have all the timing correctly. I generate test bar using these timings and I'm able to talk to the encoder and display it on the monitor. however axi4s_to_video_out  does not lock. 

In chipscope, I get data coming out of video_in_to axi4s and it comes in to the FIFO in axi4s and axi4s_to_video_out but the locked signal does not exist from output synchronizer. 

I have also noticed that the eol from video_in_to axi4s does not line up with the eol in axi4s_to_video_out. Does anybody have any suggestions please? I do not have axi4-lite enabled.

 

I have read all of the forum with the exact problem, however it seems not to fix the problem for me ( the link is below).  I have seen people mentioned about FMC IMAGEON demo. however I can not find this demo anywhere since it is old. I was wondering if someone has this demo in  archive folder somewhere. I would really appreciate it. 

https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Need-a-little-help-with-the-Video-Out-core/m-p/313551#M7868

 

like I said, I'm new at FPGA and my system is kind of old design now and there are not that many tutorials anymore ( everything is vivado). I don't know how to setup axi4-lite for the VTC with EDK. Is there any tutorials how to setup axi4-lite with microblaze in EDK?

 

Capture.JPG
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33 Replies
Moderator
Moderator
2,120 Views
Registered: ‎11-09-2015

Re: axi4s_to_video_out won't lock

Hi @p.nejad,

 

The AXI4S to video out has some outputs which can help you:

  • the underflow and overflow status
  • the status output

By checking these output you might be able to find what is wrong with your system.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Participant p.nejad
Participant
2,113 Views
Registered: ‎03-09-2018

Re: axi4s_to_video_out won't lock

Hello florentw

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Moderator
Moderator
2,111 Views
Registered: ‎11-09-2015

Re: axi4s_to_video_out won't lock

Hi @p.nejad,

 

This is an output so you can use chipscope


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Participant p.nejad
Participant
2,096 Views
Registered: ‎03-09-2018

Re: axi4s_to_video_out won't lock

Hello florentw,

I do not have underflow and overflow status on my output core ILA for some reason. I have seen it in other forums that people have used it.

I can not find it anywhere in my outputs. I have checked all the signals in ILA. 

I would really appreciate it if you could share some example code please.  

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Moderator
Moderator
2,079 Views
Registered: ‎11-09-2015

Re: axi4s_to_video_out won't lock

Hi @p.nejad,

 

Did you connect the underflow and overflow from the AXI4S to Video Out to your ILA?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Participant p.nejad
Participant
2,058 Views
Registered: ‎03-09-2018

Re: axi4s_to_video_out won't lock

Hello Florentw,

I have connected empty and wr_error and rd_error to ILA as shown in attachment. 

I still have not figured it out yet.  

Capture1.JPG
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Participant p.nejad
Participant
2,030 Views
Registered: ‎03-09-2018

Re: axi4s_to_video_out won't lock

Hello,

I can see that the output of axi4s_video_out is not sync with my timing source. the eol from vid_in_axi4s does not align with eol from axi4s_video_out. but I don't know how to make them align. Do you have any recommendation please?

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Moderator
Moderator
2,018 Views
Registered: ‎11-09-2015

Re: axi4s_to_video_out won't lock

HI @p.nejad,

 

To align them you need to use the fsync input with a timing controller.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Participant p.nejad
Participant
2,006 Views
Registered: ‎03-09-2018

Re: axi4s_to_video_out won't lock

Hello,
I have fsync connected to fv_re . I have also noticed on the oscilloscope that Tuser only exists with fv_re every third frame. I have no idea why it does not it does recognize every frame.
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Moderator
Moderator
1,879 Views
Registered: ‎11-09-2015

Re: axi4s_to_video_out won't lock

Hi @p.nejad,

 

Yes you might need to investigate that. It could be a misconfiguration somewhere in the frame size?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Moderator
Moderator
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Registered: ‎11-09-2015

Re: axi4s_to_video_out won't lock

Hi @p.nejad,

 

Do you have any updates on this subject?

 

If everything is clear for you, please kindly close the topic by marking a reply as accepted solution.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Participant p.nejad
Participant
1,819 Views
Registered: ‎03-09-2018

Re: axi4s_to_video_out won't lock

Hello florentw,

Thank you very much for following up. unfortunately, i'm still struggling with this.

In simulation I get the intc_if(8) after the 4th frame and all my vblank,hblank,vsync,hsync are in sync. I still do not get the lock. I also noticed that FIFO_rst is set every other frame in axi4s_to_video_out. Do you have any suggestion please? It's really frustrating right now. I've been working 12hrs days with no luck or lock. 

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Participant p.nejad
Participant
1,816 Views
Registered: ‎03-09-2018

Re: axi4s_to_video_out won't lock

 
Capture2.JPG
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Moderator
Moderator
1,779 Views
Registered: ‎11-09-2015

Re: axi4s_to_video_out won't lock

HI @p.nejad,

 

Now you need to check the underflow signal of the AXI4S to video out. It might be that your data are not fast enough for the timing.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Scholar watari
Scholar
1,772 Views
Registered: ‎06-16-2013

Re: axi4s_to_video_out won't lock

Hi @p.nejad

 

Did your design have front porch of vsync ?

It doesn't seem to have any front porch of vsync.

 

Can you modify video parameter, if my understanding is correct ?

 

Best regards,

 

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Participant p.nejad
Participant
1,759 Views
Registered: ‎03-09-2018

Re: axi4s_to_video_out won't lock

Hi ,
I do not have underflow signal in my axi4s to video out. I have checked all the signals. I'm using LogiCORE IP AXI4-S Vid Out v2.01a.
my sensor is 1280x960 and I'm taking 720x578 from that. i'm setting my vsync to start at line 580 and end at 585. so my front porch is 2 pixel. Do you think this is a problem?
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Scholar watari
Scholar
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Registered: ‎06-16-2013

Re: axi4s_to_video_out won't lock

Hi @p.nejad

 

I'd like to confirm your waveform.

Would you show me expanded waveform around VSync ? (HSYNC, VSYNC, HBLANK, VBLANK, Active Video and so on)

 

Best regards,

 

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Participant p.nejad
Participant
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Registered: ‎03-09-2018

Re: axi4s_to_video_out won't lock

Hello Watari,

Thanks for you help!

I added an attachment with expanded waveforms. Please let me know if you need any more specific area. 

capture3.jpg is the start of the frame and it shows the first line. 

capture4.jpg is the start of the frame with first 3 lines. 

capture5.jpg is the start of the line more zoomed in. Please take a look at Tlast and eol with hblank??? 

capture6.jpg is the end of FV. 

Please let me know if you can make sense of what I'm doing wrong. 

 

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Scholar watari
Scholar
1,681 Views
Registered: ‎06-16-2013

Re: axi4s_to_video_out won't lock

Hi @p.nejad

 

Could you tell me the followings to make sure waveform ?

 

- Clock frequency

- (At least) width of parameter. (ex. HSYNC width, VSYNC width and so on)

 

Best regards

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Participant p.nejad
Participant
1,815 Views
Registered: ‎03-09-2018

Re: axi4s_to_video_out won't lock

Hi watari,

clock frequency is 27 MHz.

Hblank = ~ LV . the period of the LV is 32us which is 26.666us of active pixels (720 pixels) and  5.333 us hblank( 864-720).

 hsync  starts at pixel 732 and ends at pixel 796 which is 64 pixels. (2.33us)

 

Vblank = ~FV . the period of the FV is 20ms which is 18.496ms of active lines (576 lines) and 1.53ms vblank (625 - 576)

vsync starts at line 580 and ends at line 585 which is 5 lines. ( I just noticed that in simulation my vsync is only 32us wide which is 1 line instead of 5 lines) this means that there is something wrong with my line counter, Correct?

 

active video =  FV & LV. 

 

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Scholar watari
Scholar
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Registered: ‎06-16-2013

Re: axi4s_to_video_out won't lock

Hi @p.nejad

 

I guess the route cause is wrong relationship between sof and eol (tlast).

Would you show me the followings to make sure it ?

 

- intc_if value on VTC (if you implement vtc IP)

- status value on AXI4S_VID_OUT

- all video input signals on VID_IN_AXI4S (if you implement. But I'm sure that a relationship of all input video signals are wrong. So that, vid_in_axi4s output wrong sof and eof.)

 

If you can not find these signals (intc_if and status), would you show me your Vivado version and IP version ?

 

Best regards,

 

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Participant p.nejad
Participant
1,789 Views
Registered: ‎03-09-2018

Re: axi4s_to_video_out won't lock

Hello Watati,

 

I'm using ISE 14.7 and  I'm using LogiCORE IP Video In AXI4-S v2.01a . I do not have axi-lite enabled so I do not get any of status signals. 

I have used VTC before and it did not work so right now I'm creating FV and LV myself. attached is the vhdl code with some comments of how I'm creating these signals and the top level of Video in to axi4 stream. I'm using the same signal on VTG for axi4 stream to video out. 

Again, Thank you very much for you help. 

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Scholar watari
Scholar
1,782 Views
Registered: ‎06-16-2013

Re: axi4s_to_video_out won't lock

Hi @p.nejad

 

I'm not sure. But if you can find the following signals on each IPs, would you show me it ?

 

- status (My design (Vivado 2017.4) has this port on axi4s_video_out)

 

Also, if possible, would you show me your block diagram, too ?

I'd like to find out the route cause. But I need your block design. (I'm not enough knowledge of VHDL.)

 

Best regards,

 

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Participant p.nejad
Participant
1,760 Views
Registered: ‎03-09-2018

Re: axi4s_to_video_out won't lock

Hi Watari,

I attached the block diagram. On the earlier messages I have attached how I'm creating the FV/LV/Hsyn/Vsync. 

We have the DDR section and encoder section working with our own debayer and RGB2ycrcb circuits in the previous version(not very satisfied with quality image). now I'm trying to add xilinx IP blocks for the new rev. 

I also checked and there is no status signal in the IP. 

 

blockdiagram.JPG
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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

Re: axi4s_to_video_out won't lock

Hello,

What is the purpose of converting from video interface (i.e. hblank/vblank) to AXI Stream back to video interface? Why not just take the output from AFIFO directly to your PAL encoder?
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Scholar watari
Scholar
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Registered: ‎06-16-2013

Re: axi4s_to_video_out won't lock

Hi @p.nejad

 

My opinion is same as @bwiec .

However, if there is some design between video-in to AXI4S and AXI4S, I suggest to change the followings.

 

- Change the connection of all video control signal from "VTC=>AXI4S-Video-out" anf "VTC=>Video-in-AXI4S".

 

Because of you need to take care AXI4Stream signals to communicate between "Video-in to AXI4S" and "AXI4S to Video-out" to lock some signals.

 

In your case, the relationship between sof and eol is wrong. So that, "AXI4S to Video-out" can not be locked.

Could you make sure this relationship ?

If it is difficult, would you try my suggestion ?

 

[Signals]

SOF : Start of frame. It should prepare 1pulse signal, which is synchronized by 1st active data.

EOL: End of line. It should prepare 1 pulse signal, which is synchronized by last active data of each line.

 

Best regards,

Highlighted
Participant p.nejad
Participant
1,732 Views
Registered: ‎03-09-2018

Re: axi4s_to_video_out won't lock

Hi Bwiec,
This is the first step, I’m going to add CFA and CCM and RGB2YCrCb after I get the lock
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Participant p.nejad
Participant
1,713 Views
Registered: ‎03-09-2018

Re: axi4s_to_video_out won't lock

Hi Watari,

Thanks for explanation.

EOL: End of line. It should prepare 1 pulse signal, which is synchronized by last active data of each line.

I think that's where my mistake is. I set my end of line with the blanking. 

I will try this in the morning and give you the result as I already left work.

Thanks again,

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

Re: axi4s_to_video_out won't lock

Ah okay, I see.

So one more question about the architecture: Why not use the AXI VDMA in place of AFIFO and Vidin to AXI4s?

The problem with the setup as-is is that the AXIS2VidOut core will only have limited ability to throttle upstream on the AXIS interface because your AFIFO has no backpressure capability. The AXI VDMA will fix that.

Otherwise, you should make sure the AXIS2VIDOut core is in slave mode and that you connect the vtg_ce signal back to the VTC.
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