08-07-2019 02:49 PM
I am using Native Video Input Interface with hdmi_tx_ss at 4 pixel per clock, and I am generating the video sync signals:
for 1080p60 timing is:
Front Porch = 88px
Sync Width = 44px
Back Porch = 148px
since input is 4 pixel per clock video_clk is pixel clok divided by 4
to generate video sinc signals with my video_clk I just divide this values by 4, and it works
Front Porch = 88px / 4 = 22
Sync Width = 44px / 4 = 11
Back Porch = 148px / 4 = 37
but for 720p60
Front Porch 110px / 4 = 27.5
Sync Width 40px / 4 = 10
Back Porch 220px / 4 = 55
counter cannot count 27.5 clocks
Any idea how this problem can be resolved?
08-09-2019 12:34 AM
I assume you are using the Xilinx VIdeo timing controller? If yes, this is not supported. The resolution (all parameters) need to be dividable by the PPC.
08-09-2019 06:31 AM
no, I am not using Xilinx VIdeo timing controller, I use my code,
but, even if I generate sync signals on double video clock, I guess it won't resolve the problem since the input is clocked on video clock.
so, no solution for 4px/clk 720p60?
08-09-2019 10:18 AM
It might work if you find a timing which is dividable.
Maybe you can move the sync slightly
08-14-2019 01:26 AM
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