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Registered: ‎09-17-2018

mipi CSI-2 RX, no frame received


We have a system as follows: sensor -> serdes -> ISP -> FPGA( mipi CSI-2 RX -> FramebufferWrite -> PS).

We know the CSI-2 stream generated from ISP has the following properties:

  • video format: 1920x1280, 50Hz
  • color space: RGB888
  • linerate: 1.5Gbps
  • 4 lanes
  • non-continuous clock mode
  • only use virtual channel 0

So in Vivado we configured the mipi CSI-2 RX IP as: 1500Mbps, RGB888, 4 lanes. We use 200MHz as video_aclk.


However, when using baremetal software to test the video, we are getting a lot of error interrupts from the CSI-2 receiver:

+===> Other Errors detected.
Stop Error 
+===> DPHY Level Error detected.
Start of Transmission Error
+===> Packet Level Error detected.
VC3 Frame Sync Error 
VC2 Frame Sync Error 
VC1 Frame Sync Error 
+===> Packet Level Error detected.
2 bit ECC Error 
There is no frame received event detected. We used a systme ILA to check the output of CSI-2 RX,  but it shows there is no active axi stream generated.
Anyone knows where the problem could be? (we are using Vivado 2018.3, processor is zu5ev)


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Xilinx Employee
Xilinx Employee
Registered: ‎03-30-2016

Re: mipi CSI-2 RX, no frame received

Hello @xinyiz 

1. Is it UltraScale+ device (I believe so) , or is it 7-series ?

2. Could you please share MIPI CSI-2 RX register dump ?
    # and MIPI D-PHY register dump if this is also accessible ?

3. I am suspecting this is Signal-Integrity problem since Interupt register mentioned:
        Start of Transmission Error
        2 bit ECC Error

    Could you please share your Oscilloscope capture of your clock and data lane during LP --> HS transition ?


Thanks & regards

Registered: ‎10-04-2017

Re: mipi CSI-2 RX, no frame received

Hi @xinyiz,


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