07-28-2019 06:14 AM
We have a system as follows: sensor -> serdes -> ISP -> FPGA( mipi CSI-2 RX -> FramebufferWrite -> PS).
We know the CSI-2 stream generated from ISP has the following properties:
So in Vivado we configured the mipi CSI-2 RX IP as: 1500Mbps, RGB888, 4 lanes. We use 200MHz as video_aclk.
However, when using baremetal software to test the video, we are getting a lot of error interrupts from the CSI-2 receiver:
07-29-2019 07:30 PM
1. Is it UltraScale+ device (I believe so) , or is it 7-series ?
2. Could you please share MIPI CSI-2 RX register dump ?
# and MIPI D-PHY register dump if this is also accessible ?
3. I am suspecting this is Signal-Integrity problem since Interupt register mentioned:
Start of Transmission Error
2 bit ECC Error
Could you please share your Oscilloscope capture of your clock and data lane during LP --> HS transition ?
Thanks & regards
08-08-2019 10:36 AM
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