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Contributor
Contributor
456 Views
Registered: ‎09-17-2018

mipi csi-2 rx subsystem: only receive frames when fpga is powered and programmed first

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Hi @karnanl ,

This is a continuation of the following topic:

https://forums.xilinx.com/t5/Video/mipi-csi-2-rx-subsystem-only-receive-frames-when-fpga-is-powered/m-p/990105

I'm still struggling with the CSI-2 video. This time I got more debug information so maybe anyone can help me understand where the problem is. We have a camera which outputs CSI-2 video, and we use a design containing CSI2-RX, VDMA, PS to receve video on Zynq. 

The current problem is:

  1. We can only receive frames when power and program Zynq first and the start the camera.
  2. If in a reverse order, we cannot receive video at the beginning. But if we soft reset the camera board(there is a soft reset button on that board), we get the frames again.

The latter situation makes me believe that even if CSI-RX lanes are not initialized well at the beginning when the camera has started streaming, it is not broken and is still waiting for the next LP-11 state. That's why by resetting the camera, we received the frames again.

Previously I thought the CSI-TX only sends LP-11 state after reset, but by checking the signals using an osiloscope, I found it is sending LP-11 data between every burst of HS video data, and they are all of the same length(approx 20ms).

This is the data lane signal we got immediately after reset:

CSI_after_reset.png

By zooming in, we can see there is LP-11 state between each HS burst, and they are all around 20ms.

LP11_intervals.png

According to the diagram in PG202, the physical lanes of CSI2-RX should be able to initialized as long as it receives the first LP-11 state, regardless of what is on the lane before:

dphy.png

So I don't understand where the problem is. And our requirement is to be able to receive video even if the camera starts streaming first. Anybody has any idea on this?

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Xilinx Employee
Xilinx Employee
414 Views
Registered: ‎03-30-2016

Re: mipi csi-2 rx subsystem: only receive frames when fpga is powered and programmed first

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Hello @xinyiz 


>We can only receive frames when power and program Zynq first and the start the camera.

If you start Zynq first, and Camera later, MIPI RX will observe 20ms LP-11 sent by your Camera,
so MIPI RX initialization will be completed.

>If in a reverse order, we cannot receive video at the beginning.
>But if we soft reset the camera board(there is a soft reset button on that board), we get the frames again.
>The latter situation makes me believe that even if CSI-RX lanes are not initialized well at the beginning
>when the camera has started streaming, it is not broken and is still waiting for the next LP-11 state.
>That's why by resetting the camera, we received the frames again.

I believe your understanding above is correct.
-- To confirm your understanding, you may need to check INIT_DONE register from MIPI D-PHY RX IP. (Please see PG202 Chapter2 for detailed register address). Please check all data lanes and clock lane.

>Previously I thought the CSI-TX only sends LP-11 state after reset, but by checking the signals using an osiloscope,
>I found it is sending LP-11 data between every burst of HS video data, and they are all of the same length(approx 20ms).

Please see the following describtion from MIPI spec. Please notice that 100us is the min TINIT time required for initialization.

XF_DPHY_TINIT.png

According to your oscilloscope waveform.
1. LP-11 between HS data is 20ms
2. After reset tha LP-11 period is about the same 20ms. (LP-00 at the first will not disturb initialization process )

 

Suggest to start Zynq first to follow MIPI D-PHY spec requirement.
I would not start camera first, because if you start your camera first,
there would be a high probability that MIPI RX will see HS data (not LP-11) when they start initialization.


Thanks & regards
Leo

2 Replies
Xilinx Employee
Xilinx Employee
415 Views
Registered: ‎03-30-2016

Re: mipi csi-2 rx subsystem: only receive frames when fpga is powered and programmed first

Jump to solution

Hello @xinyiz 


>We can only receive frames when power and program Zynq first and the start the camera.

If you start Zynq first, and Camera later, MIPI RX will observe 20ms LP-11 sent by your Camera,
so MIPI RX initialization will be completed.

>If in a reverse order, we cannot receive video at the beginning.
>But if we soft reset the camera board(there is a soft reset button on that board), we get the frames again.
>The latter situation makes me believe that even if CSI-RX lanes are not initialized well at the beginning
>when the camera has started streaming, it is not broken and is still waiting for the next LP-11 state.
>That's why by resetting the camera, we received the frames again.

I believe your understanding above is correct.
-- To confirm your understanding, you may need to check INIT_DONE register from MIPI D-PHY RX IP. (Please see PG202 Chapter2 for detailed register address). Please check all data lanes and clock lane.

>Previously I thought the CSI-TX only sends LP-11 state after reset, but by checking the signals using an osiloscope,
>I found it is sending LP-11 data between every burst of HS video data, and they are all of the same length(approx 20ms).

Please see the following describtion from MIPI spec. Please notice that 100us is the min TINIT time required for initialization.

XF_DPHY_TINIT.png

According to your oscilloscope waveform.
1. LP-11 between HS data is 20ms
2. After reset tha LP-11 period is about the same 20ms. (LP-00 at the first will not disturb initialization process )

 

Suggest to start Zynq first to follow MIPI D-PHY spec requirement.
I would not start camera first, because if you start your camera first,
there would be a high probability that MIPI RX will see HS data (not LP-11) when they start initialization.


Thanks & regards
Leo

Moderator
Moderator
351 Views
Registered: ‎11-09-2015

Re: mipi csi-2 rx subsystem: only receive frames when fpga is powered and programmed first

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Hi @xinyiz 

Do you have any update on this? Was @karnanl 's enough for you?

If your question is answered or your issue is solved, please kindly mark the response which helped as solution (click on "Accept as solution" button below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Thanks and Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
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