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Contributor
Contributor
7,454 Views
Registered: ‎05-22-2008

strange error message while using blackbox!!!

hi

 

i get this strange error message when i try to add black box and specify the vhdl design file.

 

can't figureout how to deal with this problem.

 

can somebody help...

 

screenshot.JPG
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7 Replies
Xilinx Employee
Xilinx Employee
7,446 Views
Registered: ‎11-28-2007

Re: strange error message while using blackbox!!!

It looks like that you have syntax error in your VHDL file. Have you tried checking syntax on it using other compilers (e.g. modelsim, xst, etc) it?

 

Cheers,

Jim

Cheers,
Jim
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Contributor
Contributor
7,435 Views
Registered: ‎05-22-2008

Re: strange error message while using blackbox!!!

hi

 

i have checked the syntax using ISE, it didn't show any error. This file was generated by core generator.

 

sandeep

Message Edited by sandeep.ism on 06-22-2009 09:25 PM
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Voyager
Voyager
7,430 Views
Registered: ‎05-09-2008

Re: strange error message while using blackbox!!!

Hi sandeep.is,

 

I too often I have had that type of error, specially if the file .vhd / .v is very long (like FFT, etc).

 

I solved by creating a "wrapper" for the form .vhd / .v.

 

Check in the System Generator guide :
 
"Black Box Tutorial Example 2: Importing a Core Generator Module that Needs a VHDL Wrapper to Satisfy Black Box HDL Requirements"

 

 Kappa.

Message Edited by secureasm on 06-22-2009 11:57 PM
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Contributor
Contributor
7,408 Views
Registered: ‎05-22-2008

Re: strange error message while using blackbox!!!


@secureasm

I think u r right since this file is large,
but i could not follow the tutorial since the wrapper file (.vhd) created
was not as shown in the example. It does not has the guidelines for pasting component declaration, etc. from the .vho file.
I tried to do it myself but it did not helped and i faced the same error.

sandeep
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Voyager
Voyager
7,396 Views
Registered: ‎05-09-2008

Re: strange error message while using blackbox!!!

Hi sandeep,

 

Please send "entity" statement of your vhdl code, I show you how to write the wrapper ...

 

Kappa.

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Contributor
Contributor
7,394 Views
Registered: ‎05-22-2008

Re: strange error message while using blackbox!!!

hi
thanks secureasm
here is the entity statement :

entity tcc_decoder_3gpp_v3_1 is
port (
fd_in : in STD_LOGIC := 'X';
rfd : out STD_LOGIC;
rdy : out STD_LOGIC;
clk : in STD_LOGIC := 'X';
rffd : out STD_LOGIC;
block_size : in STD_LOGIC_VECTOR ( 12 downto 0 );
d_in : in STD_LOGIC_VECTOR ( 14 downto 0 );
iterations : in STD_LOGIC_VECTOR ( 3 downto 0 );
d_out : out STD_LOGIC_VECTOR ( 0 downto 0 )
);
end tcc_decoder_3gpp_v3_1;



sandeep

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Voyager
Voyager
7,374 Views
Registered: ‎05-09-2008

Re: strange error message while using blackbox!!!

Hi sandeep,

 

Sorry for a delay ...

 

This is a code of wrapper :

 

 

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:00:16 26/06/2009
-- Design Name:
-- Module Name: tcc_decoder_3gpp_v3_1_wrapper - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity tcc_decoder_3gpp_v3_1_wrapper is
port (
ce : in std_logic;
clk : in std_logic;

fd_in : in std_logic;
block_size : in std_logic_vector ( 12 downto 0 );
d_in : in std_logic_vector ( 14 downto 0 );
iterations : in std_logic_vector ( 3 downto 0 );

rfd : out std_logic;
rdy : out std_logic;
rffd : out std_logic;
d_out : out std_logic_vector ( 0 downto 0 )
);
end tcc_decoder_3gpp_v3_1_wrapper;

architecture Behavioral of tcc_decoder_3gpp_v3_1_wrapper is

--
-- Generate core with "Coregen", add pin "CE" to core for use in System Generator.
--

component tcc_decoder_3gpp_v3_1
port (
ce : in std_logic; -- Default pin for system generator, please generate core with "CE" pin.
clk : in std_logic; -- Default pin for system generator.

fd_in : in std_logic;
block_size : in std_logic_vector ( 12 downto 0 );
d_in : in std_logic_vector ( 14 downto 0 );
iterations : in std_logic_vector ( 3 downto 0 );

rfd : out std_logic;
rdy : out std_logic;
rffd : out std_logic;
d_out : out std_logic_vector ( 0 downto 0 )
);
end component;

-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of tcc_decoder_3gpp_v3_1: component is true;

begin

TCC_DECODER : tcc_decoder_3gpp_v3_1

port map (
ce => ce_int,
clk => clk,

fd_in => fd_in,
block_size => block_size,
d_in => d_in,
iterations => iterations,

rfd => rfd,
rdy => rdy,
rffd => rffd,
d_out => d_out
);

end Behavioral;

When you generate a IP Core with Coregen for System Generator do not forget the pin "CE".

 

I have attached the file .mdl with IP core imported.

 

Kappa

Message Edited by secureasm on 06-26-2009 12:10 AM