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Observer bva_rzn
Observer
799 Views
Registered: ‎07-04-2017

stream to address map ddr

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Hi,

 

Vivado 2016.4, board VC707.

 

The test pattern generator generates an image of 720 by 576. One pixel takes 8 bits. This image comes through VDMA and MIG in DDR. VDMA is configured for writing only. The base address of MIG is 0x90000000. Gen-lock is disabled.

Question: By what addresses are the image bytes located in DDR memory? Do I understand correctly that 720 by 576 bytes should be located at the addresses 0x90000000 ... 0x90065400?

I connected the ILA to the AXI4 vdma bus. Judging by the addresses on the address bus, bytes are located in the memory blocks of 714 bytes. In the SDK on the memory tab, bytes from the AXI bus to ILA are the same as in memory.

Is it possible to arrange the bytes of the entire image in memory consecutively?

 

Best regards.

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Observer bva_rzn
Observer
1,057 Views
Registered: ‎07-04-2017

Re: stream to address map ddr

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The question is closed. Incorrectly calculated Horizontal Size for a given image size in the settings of vdma.

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Scholar watari
Scholar
792 Views
Registered: ‎06-16-2013

Re: stream to address map ddr

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Hi @bva_rzn

 

What format do you use ? RGB 888 ? Y 8 ? YUV422 ?

 

I guess you use RGB888 format.

If my understanding is correct, 720 by 576 bytes is located at the addresses 0x90000000 ... 0x9012EC00.

 

Best regards,

 

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Observer bva_rzn
Observer
785 Views
Registered: ‎07-04-2017

Re: stream to address map ddr

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Sorry,

 

format image 8-bit grayscale.

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Observer bva_rzn
Observer
1,058 Views
Registered: ‎07-04-2017

Re: stream to address map ddr

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The question is closed. Incorrectly calculated Horizontal Size for a given image size in the settings of vdma.

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