UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Visitor chunjiew
Visitor
391 Views
Registered: ‎01-19-2019

tuser is kept more than one cycle in mipi csi-2 rx subsystem

Jump to solution

From the last thread https://forums.xilinx.com/t5/Video/mipi-csi-2-rx-subsystem-only-receive-frames-when-fpga-is-powered/td-p/951571, the CRC and ECC are fixed.

When capturing the data output from the mipi csi-2 rx subsystem, the tuser is kept more than ONE clock cycle, which will corrupt the later IP such as axis_subset_convert. 

wave.jpg

Are there any ideas why the tuser is kept more than 1 clock cycle?

 

Thank you for your time and any help is appreciated.

Regards,

Chunjie

1 Solution

Accepted Solutions
Moderator
Moderator
191 Views
Registered: ‎11-09-2015

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

Jump to solution

Hi @chunjiew ,

Do you have any updates on this? Is everything clear enough for you?


If your question is answered or your issue is solved, please mark the response which helped as solution (click on the button "Accept as solution" below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
8 Replies
Highlighted
Visitor chunjiew
Visitor
360 Views
Registered: ‎01-19-2019

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

Jump to solution

Hi @karnanl

Could you take some time to check the issue about tuser signal, which is quite strange? I use the evaluation license.

From the register status, as follows, the IP should work well.

mip-reg.png

Your time is quite appreciated.

Thanks,

chunjie

0 Kudos
Visitor wjn0719
Visitor
337 Views
Registered: ‎11-15-2018

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

Jump to solution

Forgot the IP processing path: MIPI CSI-2 RX -> axis_sub_converter -> demosaic -> VDMA. This path is just for debugging. It seems that demosaic cannot handle bad frame, such as the two consecutive tusr.

Your ideas are appreciated.

mipi_process.png

Thanks

0 Kudos
Xilinx Employee
Xilinx Employee
307 Views
Registered: ‎03-30-2016

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

Jump to solution

Hello @chunjiew 

tuser is a multiple bits signal. ( 96bits for 2018.1 MIPI CSI-2 RX SUbsystem )
Could you please check your RTL connectivity ?


tuser[0] should only "high" for one clock every frame (tuser[0] == Start of Frame).
Please let me know if tuser[0] is behave incorrectly on your system, we will need to do some debugging.

 

Thanks and regards
Leo

Visitor chunjiew
Visitor
286 Views
Registered: ‎01-19-2019

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

Jump to solution

Hi @karnanl

 

The issue has been fixed as the later demosaic is not working well, so the stream stops.

 

Thanks again,

Chunjie

Moderator
Moderator
278 Views
Registered: ‎11-09-2015

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

Jump to solution

HI @chunjiew ,

I do not think we can say that the deinterlacer is not working well. This is an expected behaviour, the deinterlacer expect full frames and is not designed to handle bad frames.


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Xilinx Employee
Xilinx Employee
260 Views
Registered: ‎03-30-2016

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

Jump to solution

Hello @chunjiew 

  1. tuser is a 96 bits of signal. So if your design only enabled tuser[0] in the GUI,
    Please enabled all of 96 bits and could you please share the ILA with us ?
    by enabling all the bits, we can see all the information such as Data type, word count etc

  2. (a) Did you enable “Embedded non-image interface” in your design ?
    (b) Do you have embedded non-image data coming from your sensors ?
    -- If the answer : (a) No, (b) yes
        then this might occurs depends on sensor data.

  3. One more thing, is your sensor has multiple VC of video stream ?
    If yes , please capture TDEST on ILA too.

 

Thanks & regards
Leo

0 Kudos
Moderator
Moderator
192 Views
Registered: ‎11-09-2015

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

Jump to solution

Hi @chunjiew ,

Do you have any updates on this? Is everything clear enough for you?


If your question is answered or your issue is solved, please mark the response which helped as solution (click on the button "Accept as solution" below the reply)

If this is not solved/answered, please reply in the topic giving more information on your current status.

Best Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Visitor chunjiew
Visitor
162 Views
Registered: ‎01-19-2019

Re: tuser is kept more than one cycle in mipi csi-2 rx subsystem

Jump to solution

Hi @karnanl  and @florentw 

 

Sorry for the late replay, and many thanks for your answer. The solution has been accepted.

 

Regards,

Chunjie